US 10,269,440 B2Granted

Flash memory array with individual memory cell read, program and erase

AssigneesSilicon Storage Technology, Inc., The Regents of the University of California

InventorsXinjie Guo, Farnood Merrikh Bayat, Dmitri Strukov, Nhan Do, Hieu Van Tran, Vipin Tiwari

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Abstract

A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

Claims7

Dependent claims

A memory device, comprising:

a substrate of semiconductor material;
a plurality of memory cells formed on the substrate and arranged in an array of rows and columns, wherein the rows of the memory cells are arranged in alternating even and odd numbered rows;
each of the memory cells includes:
spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between,
a floating gate disposed over and insulated from a first portion of the channel region adjacent the source region, and
a control gate disposed over and insulated from a second portion of the channel region adjacent the drain region;
each of the rows of memory cells includes a source line that electrically connects together all the source regions for the row of memory cells;
each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells;
each of the columns of memory cells includes a first control gate line that electrically connects together all the control gates of the memory cells in the column of memory cells that are in the odd numbered rows of the memory cells and that is not electrically connected to the control gates of the memory cells in the column of memory cells that are in the even numbered rows of the memory cells;
and
each of the columns of memory cells includes a second control gate line that electrically connects together all the control gates of the memory cells in the column of memory cells that are in the even numbered rows of the memory cells and that is not electrically connected to the control gates of the memory cells in the column of memory cells that are in the odd numbered rows of the memory cells.

8 more elements

A method of erasing a selected memory cell of a memory device, wherein the memory device comprises:

a substrate of semiconductor material;
a plurality of memory cells formed on the substrate and arranged in an array of rows and columns, wherein the rows of the memory cells are arranged in alternating even and odd numbered rows, and wherein one of the plurality of memory cells is a selected memory cell;
each of the memory cells includes:
spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between,
a floating gate disposed over and insulated from a first portion of the channel region adjacent the source region, and
a control gate disposed over and insulated from a second portion of the channel region adjacent the drain region;
each of the rows of memory cells includes a source line that electrically connects together all the source regions for the row of memory cells;
each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells;
each of the columns of memory cells includes a first control gate line that electrically connects together all the control gates of the memory cells in the column of memory cells that are in the odd numbered rows of the memory cells and that is not electrically connected to the control gates of the memory cells in the column of memory cells that are in the even numbered rows of the memory cells;
and
each of the columns of memory cells includes a second control gate line that electrically connects together all the control gates of the memory cells in the column of memory cells that are in the even numbered rows of the memory cells and that is not electrically connected to the control gates of the memory cells in the column of memory cells that are in the odd numbered rows of the memory cells;
the method comprising:
applying a positive voltage to one of the first or second control gate lines that is electrically connected to the control gate of the selected memory cell, and a ground voltage to all the others of the first and second control gate lines;
applying a ground voltage to one of the source lines that is electrically connected to the source region of the selected memory cell, and a positive voltage to all the others of the source lines;
and
applying a ground voltage to all of the bit lines.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/374,588Filed 9 Dec 2016 · us provisional application
Priority: 17 May 2016
Published: US 2017/0337980 A123 Nov 2017
Granted: 23 Apr 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

G11C 16/3431
Disturbance prevention or evaluation; Refreshing of disturbed memory data: circuits or methods to detect disturbed nonvolatile memory cells, e.g.…
G11C 7/18
Arrangements for writing information into, or reading information out from, a digital store: bit line organisation; Bit line lay-out
G11C 8/14
Arrangements for selecting an address in a digital store: word line organisation; Word line lay-out
G11C 16/0425
Comprising cells containing floating gate transistors: comprising cells containing a merged floating gate and select transistor