Variable bandwidth filter
AssigneesNational Technology & Engineering Solutions of Sandia, LLC, Jose Silva-Martinez, John Mincey, Eric Su
InventorsChristopher T. Rodenbeck, Jose Silva-Martinez, John Mincey, Eric Su
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Abstract
A variable bandwidth filter is described herein, wherein a bandwidth of a passband of the variable bandwidth filter is dynamically tunable. The variable bandwidth tuner is implemented on a CMOS chip, and acts to filter analog signals. The variable bandwidth filter comprises a plurality of finite impulse response (FIR) filters, wherein each FIR filter comprises a plurality of tunable transconductors. The tunable transconductors are tunable in their gain.
Claims16
A semiconductor chip comprising:
- a variable bandwidth filter that is configured to filter an analog signal, wherein a bandwidth of a passband of the variable bandwidth filter is dynamically programmable, the variable bandwidth filter comprising a transconductor, the transconductor comprising:
- a differential pair of transistors comprising a first transistor and a second transistor, the first transistor has a first drain, the second transistor has a second drain;
- and
- a plurality of tuning transistors that are placed across the first drain of the first transistor and the second drain of the second transistor, wherein a first tuning transistor in the tuning transistors comprises a source and a drain, the source of the first tuning transistor connected to the first drain of the first transistor in the differential pair of transistors, the drain of the first tuning transistor connected to the second drain of the second transistor in the differential pair of transistors.
A method comprising:
- forming a variable bandwidth filter on a semiconductor chip, wherein a bandwidth of a passband of the variable bandwidth filter is dynamically tunable, wherein forming the variable bandwidth filter comprises forming a transconductor, and wherein forming the transconductor comprises:
- forming a differential pair of transistors;
- and
- forming a plurality of tuning transistors that are placed across drains of the transistors in the differential pair such that a source of a first tuning transistor in the plurality of tuning transistors is connected to a drain of a first transistor in the differential pair of transistors and a drain of the first tuning transistor is connected to a drain of a second transistor in the differential pair of transistors.
Dependencies are inferred from the claim text.