US 10,257,440 B2Granted

Video matrix controller

AssigneeAten International Co., Ltd.

InventorsYi-Jen Chen, Shih-Jung Huang

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Abstract

A video matrix controller, including a receiving module, a matrix switch module and a transmission module. The matrix switch module is coupled between the receiving module and the transmission module. The receiving module includes a first port interface and a first transceiver. The first port interface receives image data and converts it to a signal, and transmits it to the first transceiver. The transmission module includes a second transceiver and a second port interface. The signal is transmitted from the first transceiver to the matrix switch module. The second transceiver receives the signal, and the second port interface converts the signal to image data and transmits it to a corresponding external display device.

Claims12

Dependent claims

A video matrix control device, comprising:

a plurality of receiving modules, each receiving module including:
a plurality of first port interfaces, each configured to receive an image data and convert it to a corresponding signal, the signal being one of a transition-minimized differential signaling (TMDS) format signal, a low-voltage differential signaling (LVDS) format signal, a serializer/deserializer (SerDes) format signal, a transistor-to-transistor logic (TTL) format signal, and a mobile high-definition link (MHL) format signal;
and
a first transceiver element which is a field-programmable gate array (FPGA), coupled to the plurality of first port interfaces, wherein the signals from the plurality of first port interfaces are transmitted to the first transceiver element;
a matrix switch module having a cross-switch unit, the cross-switch unit being one of a crosspoint switch, an FPGA, or shunts combined with a switch, wherein the first transceiver elements of the plurality of receiving modules are coupled to the matrix switch module, and the signals are transmitted to the matrix switch module via the first transceiver elements;
a plurality of transmission modules, coupled to the matrix switch module, each transmission module including:
a second transceiver element which is an FPGA, coupled to the matrix switch module, configured to receive a plurality of the signals;
a plurality of second port interfaces, coupled to the second transceiver element, each second port interface configured to convert a respective one of the signals to a corresponding image data, and to transmit the image data to a corresponding external display device;
a first number (M) of link pairs between each first transceiver element and the matrix switch module, wherein each one of the first number of link pairs is configured to fully transmit multiple signals, each signal being one of a TMDS, LVDS, SerDes, TTL, and MHL format signals;
and
a second number (N) of link pairs between each second transceiver element and the matrix switch module, wherein each one of the second number of link pairs is configured to fully transmit a signal which is one of a TMDS, LVDS, SerDes, TTL, and MHL format signals, and wherein N is greater than M,
wherein a total number of all first port interfaces of all receiving modules equal a total number of number of all second port interfaces of all transmission modules, and wherein the image data from each one of the first port interfaces is transmitted to a corresponding one of the second port interfaces via one of the first transceiver elements, the matrix switch module and one of the second transceiver elements.

9 more elements

A video matrix control device, comprising:

a receiving module, including:
a first port interface, configured to receive an image data and convert it to a corresponding signal, the signal being one of a transition-minimized differential signaling (TMDS) format signal, a low-voltage differential signaling (LVDS) format signal, a serializer/deserializer (SerDes) format signal, a transistor-to-transistor logic (TTL) format signal, and a mobile high-definition link (MHL) format signal;
and
a first transceiver element which is a field-programmable gate array (FPGA), coupled to the first port interface, wherein the signal from the first port interface is transmitted to the first transceiver element;
a matrix switch module having a cross-switch unit the cross-switch unit being one of a crosspoint switch, an FPGA, or shunts combined with a switch, wherein the first transceiver element of the receiving module is coupled to the matrix switch module, and the signal is transmitted to the matrix switch module via the first transceiver element;
a transmission module, coupled to the matrix switch module, the transmission module including:
a second transceiver element which is an FPGA, coupled to the matrix switch module, configured to receive the signal;
and
a second port interface, coupled to the second transceiver element, the second port interface configured to convert the signal to a corresponding image data, and to transmit the image data to an external display device;
a first number (M) of link pairs between the first transceiver element and the matrix switch module, wherein each one of the first number of link pairs is configured to fully transmit multiple signals, each signal being one of a TMDS, LVDS, SerDes, TTL, and MHL format signals;
and
a second number (N) of link pairs between the second transceiver element and the matrix switch module, wherein each one of the second number of link pairs is configured to fully transmit a signal which is one of a TMDS, LVDS, SerDes, TTL, and MHL format signals, and wherein N is greater than M,
wherein a total number of all first non interfaces of all receiving modules equal a total number of number of all second port interfaces of all transmission modules, and wherein the image data from each one of the first port interfaces is transmitted to a corresponding one of the second port interfaces via one of the first transceiver elements, the matrix switch module and one of the second transceiver elements.

10 more elements

A video matrix control system, comprising:

a processor;
a memory;
a receiving module, including:
a plurality of first port interfaces, each configured to receive an image data and convert it to a corresponding signal, the signal being one of a transition-minimized differential signaling (TMDS) format signal, a low-voltage differential signaling (LVDS) format signal, a serializer/deserializer (SerDes) format signal, a transistor-to-transistor logic (TTL) format signal, and a mobile high-definition link (MHL) format signal;
and
a first transceiver element which is a field-programmable gate array (FPGA), coupled to the plurality of first port interfaces, wherein the signal from the first port interface is transmitted to the first transceiver element;
a matrix switch module having a cross-switch unit, the cross-switch unit being one of a crosspoint switch, an FPGA, or shunts combined with a switch, wherein the first transceiver element of the receiving module is coupled to the matrix switch module, and the signal is transmitted to the matrix switch module via the first transceiver element;
a transmission module, coupled to the matrix switch module, the transmission module including:
a second transceiver element which is an FPGA, coupled to the matrix switch module, configured to receive the signal;
and
a plurality of second port interfaces, each coupled to the second transceiver element, each second port interface configured to convert a corresponding one of the signal to a corresponding image data, and to transmit the image data to an external display device;
wherein the receiving module, the matrix switch module and the transmission module are coupled to the processor,
wherein the matrix switch module is coupled between the receiving module and the transmission module,
a tin number (M) of link pairs between the first receiving module and the matrix switch module, wherein each one of the first number of link pairs is configured to fully transmit multiple signals, each signal being one of a TMDS, LVDS, SerDes, TTL, and MHL format signals;
and
a second number (N) of link pairs between the second receiving module and the matrix switch module, wherein each one of the second number of link pairs is configured to fully transmit a signal which is one of a TMDS, LVDS, SerDes, TTL, and MHL format signals, and wherein N is greater than M,
wherein a total number of all first port interfaces of all receiving modules equal a total number of number of all second port interfaces of all transmission modules, and wherein the image data from each one of the first port interfaces is transmitted to a corresponding one of the second port interfaces via one of the first transceiver elements, the matrix switch module and one of the second transceiver elements.

14 more elements

Dependencies are inferred from the claim text.

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Abstract

A video matrix control device, comprising:

a plurality of receiving modules, each receiving module including:
a plurality of first port interfaces, each configured to receive an image data and convert it to a corresponding signal, the signal being one of a transition-minimized differential signaling (TMDS) format signal, a low-voltage differential signaling (LVDS) format signal, a serializer/deserializer (SerDes) format signal, a transistor-to-transistor logic (TTL) format signal, and a mobile high-definition link (MHL) format signal;
and
a first transceiver element which is a field-programmable gate array (FPGA), coupled to the plurality of first port interfaces, wherein the signals from the plurality of first port interfaces are transmitted to the first transceiver element;
a matrix switch module having a cross-switch unit, the cross-switch unit being one of a crosspoint switch, an FPGA, or shunts combined with a switch, wherein the first transceiver elements of the plurality of receiving modules are coupled to the matrix switch module, and the signals are transmitted to the matrix switch module via the first transceiver elements;
a plurality of transmission modules, coupled to the matrix switch module, each transmission module including:
a second transceiver element which is an FPGA, coupled to the matrix switch module, configured to receive a plurality of the signals;
a plurality of second port interfaces, coupled to the second transceiver element, each second port interface configured to convert a respective one of the signals to a corresponding image data, and to transmit the image data to a corresponding external display device;
a first number (M) of link pairs between each first transceiver element and the matrix switch module, wherein each one of the first number of link pairs is configured to fully transmit multiple signals, each signal being one of a TMDS, LVDS, SerDes, TTL, and MHL format signals;
and
a second number (N) of link pairs between each second transceiver element and the matrix switch module, wherein each one of the second number of link pairs is configured to fully transmit a signal which is one of a TMDS, LVDS, SerDes, TTL, and MHL format signals, and wherein N is greater than M,
wherein a total number of all first port interfaces of all receiving modules equal a total number of number of all second port interfaces of all transmission modules, and wherein the image data from each one of the first port interfaces is transmitted to a corresponding one of the second port interfaces via one of the first transceiver elements, the matrix switch module and one of the second transceiver elements.

9 more elements