Wireless communications apparatus and method for performing low latency high throughput layer 2 operations

A method for use in performing wireless communications by an apparatus having at least one memory unit, a plurality of hardware accelerators coupled to the memory unit, and a control processor, the method comprising:

• sourcing/sinking packet data convergence protocol (PDCP) service data units (SDU) for transfer to/from the memory unit;
• sourcing/sinking media access control (MAC) protocol data units (PDU) for transfer to/from the memory unit;
• controlling, by the control processor in response to the first data source sourcing one or more transmit PDCP SDU for transfer to the memory unit, the plurality of hardware accelerators to:
• generate and write PDCP, radio link control (RLC), and MAC headers to the memory unit;
• and
• assemble the generated PDCP, RLC and MAC headers and the one or more transmit PDCP SDU from the memory unit into one or more transmit MAC PDU for provision to the second data sink;
• and
• controlling, by the control processor in response to the second data source sourcing one or more receive MAC PDU for transfer to the memory unit, the plurality of hardware accelerators to:
• decode PDCP, RLC and MAC headers of the one or more receive MAC PDU in the memory unit to determine locations of one or more receive PDCP SDU in the memory unit;
• and
• fetch the one or more receive PDCP SDU from the determined locations in the memory unit for provision to the first data sink.

A non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring a wireless communication computing system having at least one memory unit, a plurality of hardware accelerators coupled to the memory unit, and a control processor to perform operations comprising:

• sourcing/sinking packet data convergence protocol (PDCP) service data units (SDU) for transfer to/from the memory unit;
• sourcing/sinking media access control (MAC) protocol data units (PDU) for transfer to/from the memory unit;
• controlling, by the control processor in response to the first data source sourcing one or more transmit PDCP SDU for transfer to the memory unit, the plurality of hardware accelerators to:
• generate and write PDCP, radio link control (RLC), and MAC headers to the memory unit;
• and
• assemble the generated PDCP, RLC and MAC headers and the one or more transmit PDCP SDU from the memory unit into one or more transmit MAC PDU for provision to the second data sink;
• and
• controlling, by the control processor in response to the second data source sourcing one or more receive MAC PDU for transfer to the memory unit, the plurality of hardware accelerators to:
• decode PDCP, RLC and MAC headers of the one or more receive MAC PDU in the memory unit to determine locations of one or more receive PDCP SDU in the memory unit;
• and
• fetch the one or more receive PDCP SDU from the determined locations in the memory unit for provision to the first data sink.