Predictive rebalancing according to future usage expectations

A computing device comprising:

• an interface configured to interface and communicate with a dispersed or distributed storage network (DSN);
• memory that stores operational instructions;
• and
• processing circuitry operably coupled to the interface and to the memory, wherein the processing circuitry is configured to execute the operational instructions to:
• detect at least one available memory device within a storage unit (SU) among a plurality of memory devices within the SU including based on at least one of to receive a message from at least one of another computing device or the SU, to perform a test, to interpret a test result, or to interpret a schedule, wherein a plurality of SUs that includes the SU distributedly stores sets of encoded data slices (EDSs) associated with a data object, wherein at least some EDSs of the sets of EDSs associated with the data object that are stored in a first memory device of the plurality of memory devices within the SU are associated with a DSN address range, wherein the at least one available memory device includes a second memory device of the plurality of memory devices within the SU that is newly available within the SU having been added to the SU after the first memory device of the plurality of memory devices within the SU;
• identify storage capacities of each of the plurality of memory devices within the SU;
• identify the DSN address range associated with the SU;
• map the DSN address range to each of the plurality of memory devices within the SU based on the storage capacities of each of the plurality of memory devices within the SU that have been identified to generate a memory mapping of the plurality of memory devices within the SU including to:
• map a first DSN address sub-range of the DSN address range to the first memory device of the plurality of memory devices within the SU;
• and
• map a second DSN address sub-range of the DSN address range to the second memory device of the plurality of memory devices within the SU;
• and
• facilitate redistribution of at least one of the at least some EDSs of the sets of EDSs associated with the data object that are stored in the first memory device of the plurality of memory devices within the SU to the at least one available memory device within the SU based on the memory mapping of the plurality of memory devices within the SU.

A method for execution by a computing device, the method comprising:

• detecting, via an interface of the computing device configured to interface and communicate with a dispersed or distributed storage network (DSN), at least one available memory device within a storage unit (SU) among a plurality of memory devices within the SU, wherein a plurality of SUs that includes the SU distributedly stores sets of encoded data slices (EDSs) associated with a data object, wherein at least some EDSs of the sets of EDSs associated with the data object that are stored in a first memory device of the plurality of memory devices within the SU are associated with a DSN address range, wherein the at least one available memory device includes a second memory device of the plurality of memory devices within the SU that is newly available within the SU having been added to the SU after the first memory device of the plurality of memory devices within the SU;
• identifying storage capacities of each of the plurality of memory devices within the SU;
• identifying the DSN address range associated with the SU;
• mapping the DSN address range to each of the plurality of memory devices within the SU based on the storage capacities of each of the plurality of memory devices within the SU that have been identified to generate a memory mapping of the plurality of memory devices within the SU;
• and
• facilitating, via the interface, redistribution of at least one of the at least some EDSs of the sets of EDSs associated with the data object that are stored in the first memory device of the plurality of memory devices within the SU to the at least one available memory device within the SU based on the memory mapping of the plurality of memory devices within the SU.