Back to results
US 10,257,117 B2Granted
Distributed switch architecture
AssigneeAvago Technologies International Sales Pte. Limited
InventorsAmit Kumar, William Brad Matthews, Bruce Hui Kwan, Puneet Agarwal
Life of this patent
Estimating the term…
Abstract
A distributed switch architecture supports very high bandwidth applications. For instance, the distributed switch architecture may be implemented for cloud networks. The architecture scales by organizing traffic management components into tiled structures with distributed buffering. The tile structures are replicated and interconnected to perform transfers from ingress to egress using an interconnect bandwidth scheduling algorithm. Bandwidth scaling may be achieved by adding more tiles to achieve higher bandwidth. The interconnect in the architecture may be swapped out depending on implementation parameters, e.g., physical efficiency.
Claims18
A method comprising:
- establishing a distributed buffering architecture comprising:
- an input packet buffer in an ingress tile;
- an output packet buffer in an egress tile, the input packet buffer and the output packet buffer not being located on shared memory;
- and
- at least one buffer in a switching fabric, the at least one buffer in the switching fabric being separate from the input packet buffer and the output packet buffer and being located between an ingress and an egress of the switching fabric;
- connecting the ingress tile and the egress tile with the switching fabric;
- and
- executing a distributed bandwidth grant mechanism between the ingress tile and the egress tile, through the switching fabric,
- wherein:
- the distributed bandwidth grant mechanism comprises a store-and-forward bandwidth credit grant mechanism,
- the method further comprises tracking, with an ingress queue scheduler, active virtual output queues (VoQs) defined in the input packet buffer,
- the distributed bandwidth grant mechanism further comprises a cut through grant mechanism in which packet cells immediately begin to flow through the switching fabric to the egress tile, and
- the method further comprises:
- receiving a packet cell in a staging buffer in the ingress tile;
- and
- making an ingress-side decision on whether the packet cell is ingress-side eligible for cut through to the egress tile.
13 more elements
A machine comprising:
- an ingress tile comprising:
- an input packet buffer configured to store a whole received packet and an individual packet cell payload for an arriving packet;
- and
- a staging buffer configured to store a packet cell pointer to the packet cell payload while a cut through decision is made for the arriving packet corresponding to the individual packet cell payload;
- an egress tile comprising an output packet buffer configured to define a port-specific cut through buffer;
- a switching fabric, including at least one buffer that is separate from the input packet buffer and the output packet buffer, the at least one buffer being located between an ingress and an egress of the switching fabric, the switching fabric being configured to connect the ingress tile to the egress tile;
- and
- bandwidth allocation circuitry distributed between the ingress tile and the egress tile, the bandwidth allocation configured to:
- decide store-and-forward bandwidth credit allocation for transferring the whole received packet from the input packet buffer to the output packet buffer;
- and
- decide cut through bandwidth allocation for transferring the packet cell payload from the input packet buffer to the port-specific cut through buffer,
- wherein the input packet buffer and the output packet buffer are not located on shared memory,
- wherein cut through indicates that packet cells immediately begin to flow through the switching fabric to the egress tile, and
- wherein the bandwidth allocation circuitry is further configured to perform tracking, with an ingress queue scheduler, active virtual output queues (VoQs) defined in the input packet buffer.
11 more elements
A machine comprising:
- an ingress tile comprising:
- an input packet buffer configured to store a whole received packet and an individual packet cell payload for an arriving packet;
- and
- a staging buffer configured to store a packet cell pointer to the packet cell payload while a cut through decision is made for the arriving packet corresponding to the individual packet cell payload;
- an egress tile comprising:
- an output packet buffer configured to define a port-specific cut through buffer;
- and
- a switching fabric connecting the ingress tile to the egress tile, the switching fabric comprising:
- per-ingress tile store-and-forward buffers between an ingress and an egress of the switching fabric;
- per-ingress tile cut through buffers between the ingress and the egress of the switching fabric;
- first scheduling circuitry configured to select between the per-ingress tile store-and-forward buffers and the per-ingress tile cut through buffers to drive a first output lane to the egress tile;
- and
- second scheduling circuitry configured to select between the per-ingress tile cut through buffers, but not the per-ingress tile store-and-forward buffers, to drive a second output lane for cut through cells to the egress tile,
- wherein the input packet buffer and the output packet buffer are not located on shared memory,
- wherein cut through indicates that packet cells immediately begin to flow through the switching fabric to the egress tile, and
- wherein the machine further comprises circuitry configured to perform tracking, with an ingress queue scheduler, active virtual output queues (VoQs) defined in the input packet buffer.
13 more elements
Dependencies are inferred from the claim text.