Method and procedure for loop detection in multi-chassis link aggregation group (MCLAG) deployment within a communications system

A method, comprising:

• generating a first data unit and a second data unit at a first network device, the second data unit including a tag;
• sending, via a port of the first network device, the first data unit and the second data unit to a destination device, the port of the first network device being associated with a virtual local area network (VLAN) and being associated with a port of a multi-chassis aggregate (MCAE) interface;
• receiving, at the port of the first network device, the second data unit;
• detecting, at the port of the first network device, that the second data unit has been received at the port of the first network device using a media access control (MAC) address filter that matches a combination of a source MAC address and a destination MAC address;
• forwarding, via the first network device and after receiving the second data unit, the second data unit to a second network device associated with the VLAN and operatively coupled to the first network device;
• and
• disabling the port of the MCAE interface in response to receiving the second data unit at the port of the first network device.

An apparatus, comprising:

• a processor;
• a first multi-chassis aggregate interface (MCAE) port operatively coupled to the processor and associated with a first virtual local area network (VLAN), the first MCAE port being associated with a port of a MCAE interface;
• a second MCAE port operatively coupled to the processor and associated with a second VLAN different from the first VLAN;
• and
• a non-MCAE port operatively coupled to the processor and associated with the first VLAN;
• the processor configured to send a first data unit and a second data unit at a predetermined transmit interval via the first MCAE port, the second data unit including a tag,
• the processor configured to forward the second data unit to a network peer when the processor receives the second data unit at the first MCAE port,
• the processor configured to disable the port of the MCAE interface when the processor receives the second data unit at the first MCAE port,
• the processor configured to disable the non-MCAE port when the processor receives the second data unit at the non-MCAE port, and
• the processor configured to discard the second data unit when the processor receives the second data unit at the second MCAE port.