Apparatus and method for coarse timing and frequency synchronization

A method, comprising:

• receiving, by each of a plurality of correlation processors, a group of samples;
• generating, by each of the plurality of correlation processors, correlations for a corresponding group of samples;
• multiplying, by each of a plurality of multipliers, the correlations corresponding to one of the plurality of correlation processors by a weight, wherein the weight of each of the plurality of multipliers is uniquely different from the weights of at least two of the plurality of multipliers and the correlations;
• summing, by a summation processor, the weight multiplied correlations of the plurality of multipliers for time n, where n is an integer;
• and
• determining, by a coarse timing and coarse frequency processor, a coarse timing and a coarse frequency based on the summing of the weight multiplied correlations of the plurality of multipliers for time n.

A method of manufacturing a coarse timing and frequency synchronization apparatus, comprising:

• forming the coarse timing and frequency synchronization apparatus on a wafer or a package with at least one other coarse timing and frequency synchronization apparatus, wherein the coarse timing and frequency synchronization apparatus includes a plurality of correlation processors configured for each correlation processor to receive a group of samples and generate correlations for the received group of samples;
• a plurality of multipliers each configured to multiply the correlations corresponding to one of the plurality of correlation processors by a weight, wherein the weight of each of the plurality of multipliers is uniquely different from the weights of at least two of the plurality of multipliers and the correlations;
• a summation processor configured to sum the weight multiplied correlations of the plurality of multipliers for time n, where n is an integer;
• and a coarse timing and coarse frequency processor configured to generate a coarse timing and a coarse frequency based on the sum;
• and
• testing the coarse timing and frequency synchronization apparatus, wherein testing the coarse timing and frequency synchronization apparatus comprises testing the coarse timing and frequency synchronization apparatus using one or more electrical to optical converters, one or more optical splitters that split an optical signal into two or more optical signals, and one or more optical to electrical converters.

A method of constructing an integrated circuit, comprising:

• generating a mask layout for a set of features for a layer of the integrated circuit, wherein the mask layout includes standard cell library macros for one or more circuit features that include a coarse timing and frequency synchronization apparatus including a plurality of correlation processors configured for each correlation processor to receive a group of samples and generate correlations for the received group of samples:
• a plurality of multipliers each configured to multiply the correlations corresponding to one of the plurality of correlation processors by a weight, wherein the weight of each of the plurality of multipliers is uniquely different from the weights of at least two of the plurality of multipliers and the correlations;
• a summation processor configured to sum the weight multiplied correlations of the plurality of multipliers for time n, where n is an integer;
• and a coarse timing and coarse frequency processor configured to generate a coarse timing and a coarse frequency based on the sum;
• disregarding relative positions of the macros for compliance to layout design rules during the generation of the mask layout;
• checking the relative positions of the macros for compliance to layout design rules after generating the mask layout;
• upon detection of noncompliance with the layout design rules by any of the macros, modifying the mask layout by modifying each of the noncompliant macros to comply with the layout design rules;
• generating a mask according to the modified mask layout with the set of features for the layer of the integrated circuit;
• and
• manufacturing the integrated circuit layer according to the mask.