Linear masking circuits for side-channel immunization of advanced encryption standard hardware

A system comprising a memory, a processor coupled to the memory, and a wireless interface for allowing the processor to communicate with another device, the processor including:

• a first circuitry operable to convert a value on an input of the first circuitry into a value on an output of the first circuitry in accordance with an encryption matrix;
• a second circuitry operable to provide a sequence of pseudo-random numbers on a first output of the second circuitry and a registered copy of the sequence on a second output of the second circuitry;
• and
• a third circuitry operable to provide an XOR of a value on the output of the first circuitry and a value on the first output of the second circuitry onto an output of the third circuitry coupled to an input of a fourth circuitry.

An apparatus comprising:

• a first circuitry operable to convert a value on an input of the first circuitry into a value on an output of the first circuitry in accordance with an encryption matrix;
• a second circuitry operable to provide an inversion of a value on an input of the second circuitry to an output of the second circuitry;
• a third circuitry operable to provide an inversion of a value on an input of the third circuitry to an output of the third circuitry;
• and
• a fourth circuitry operable to perform an XOR of a value on the output of the second circuitry and a value on the output of the third circuitry,
• wherein the input of the second circuitry is coupled to at least one of:
• the input of the first circuitry and the output of the first circuitry;
• and
• wherein the input of the second circuitry is coupled to an output of a key register circuitry.