US 10,256,968 B1Granted

Systems and methods for clock and data recovery

AssigneeXilinx, Inc.

InventorsZhaoyin D. Wu, Yu Xu, Winson Lin, Yohan Frans, Geoffrey Zhang

Life of this patent

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Abstract

A clock and data recovery (CDR) circuit includes a phase detector, a digital loop filter, and a lock detector. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples. The plurality of samples are generated by sampling a received signal based on a sampling clock a sampling clock provided by a phase interpolator. The digital loop filter includes a phase path and a frequency path for providing a phase path correction signal and a frequency path correction signal based on the phase detect result signal respectively. A phase interpolator code generator generates a phase interpolator code for controlling the phase interpolator based on the phase path correction signal and frequency path correction signal. The lock detector generates a lock condition signal based on the frequency path correction signal, the lock condition signal indicating a lock condition of the CDR circuit.

Claims20

Dependent claims

A clock and data recovery (CDR) circuit, comprising:

a phase detector configured to generate a phase detect result signal in response to phase detection of a plurality of samples, the plurality of samples being generated by sampling a received signal based on a sampling clock signal provided by a phase interpolator;
a digital loop filter including:
a phase path configured to provide a phase path correction signal including a first estimate associated with a phase of the received signal based on the phase detect result signal;
a frequency path configured to provide a frequency path correction signal including a second estimate associated with a frequency of the received signal based on the phase detect result signal;
and
a phase interpolator code generator configured to generate a phase interpolator code for controlling the phase interpolator based on the phase path correction signal and frequency path correction signal;
and
a lock detector circuit configured to:
determine, using a period generator circuit, a frequency offset period based on the frequency path correction signal,
wherein the frequency offset period includes an estimate of a period of a frequency offset source in the received signal;
generate a lock condition signal based on the frequency offset period, the lock condition signal indicating a lock condition of the sampling clock signal associated with the received signal.

8 more elements

A method, comprising:

generating a plurality of samples by sampling a received signal using a sampling clock provided by a phase interpolator;
generating a phase detect result signal in response to phase detection of the plurality of samples;
generating, by a phase path of a digital loop filter, a phase path correction signal including a first estimate associated with a phase of the received signal based on the phase detect result signal;
generating, by a frequency path of the digital loop filter, a frequency path correction signal including a second estimate associated with a frequency of the received signal based on the phase detect result signal;
generating a phase interpolator code for controlling the phase interpolator based on the phase path correction signal and frequency path correction signal;
determining a frequency offset period based on the frequency path correction signal,
wherein the frequency offset period includes an estimate of a period of a frequency offset source in the received signal;
and
generating a lock condition signal based on the frequency offset period, the lock condition signal indicating a lock condition of the sampling clock associated with the received signal.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/660,141Filed 26 Jul 2017
Granted: 9 Apr 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H04L 7/0025
Correction by interpolation: interpolation of clock signal
H03L 7/0807
Details of the phase-locked loop: concerning mainly a recovery circuit for the reference signal
H03L 7/093
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: using special…
H03L 7/095
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: using a lock detector