Clock and data recovery circuit with jitter tolerance enhancement

A clock and data recovery (CDR) circuit, comprising:

• a phase detector, detecting a phase difference between an input data signal and a sampling clock signal, and generating a phase difference information signal which indicates a sign of the phase difference;
• a loop gain controller, coupled to the phase detector, detecting a first plurality of consecutive logic values in the phase difference information signal, and adjusting gain factors according to whether the first plurality of consecutive logic values are the same or alternate;
• a filter, coupled to the loop gain controller and the phase detector, filtering the phase difference information signal to generate a filtered signal according to the gain factors;
• and
• an oscillator, coupled to the filter and the phase detector, receiving the filtered signal and generating the sampling clock signal according to the filtered signal.