Decoding method, memory storage device and memory control circuit unit

A memory storage device comprising:

• a connection interface unit configured to couple to a host system;
• a rewritable non-volatile memory module comprising a plurality of physical units;
• and
• a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module,
• wherein an error checking and correcting circuit of the memory control circuit unit comprises a first decoding engine and a second decoding engine,
• wherein the memory control circuit unit is configured to issue a first read command sequence to instruct reading a first codeword from a first physical unit among the physical units,
• wherein the memory control circuit unit is further configured to perform a first parity-check operation on the first codeword to obtain a plurality of first syndromes of the first codeword before the first codeword is decoded,
• wherein the memory control circuit unit is further configured to accumulate the first syndromes to obtain a first syndrome sum,
• wherein the error checking and correcting circuit is configured to decode the first codeword by the first decoding engine in response to that the first syndrome sum is lower than a default syndrome sum,
• wherein the memory control circuit unit is further configured to issue a second read command sequence to instruct reading a second codeword from a second physical unit among the physical units,
• wherein the memory control circuit unit is further configured to perform a second parity-check operation on the second codeword to obtain a plurality of second syndromes of the second codeword before the second codeword is decoded,
• wherein the memory control circuit unit is further configured to accumulate the second syndromes to obtain a second syndrome sum,
• wherein the error checking and correcting circuit is further configured to decode the second codeword by the second decoding engine in response to that the second syndrome sum is not lower than the default syndrome sum,
• wherein a first power consumption of the first decoding engine for decoding the first codeword is lower than a second power consumption of the second decoding engine for decoding the second codeword,
• wherein the memory control circuit unit is further configured to issue a third read command sequence to instruct reading a third codeword from a third physical unit among the physical units,
• wherein the memory control circuit unit is further configured to estimate error level information of the third codeword, wherein the error level information comprises at least one of a programming count of the third physical unit, a reading count of the third physical unit, an erasing count of the third physical unit, a third syndrome sum of the third codeword, a bit error rate of the third codeword, and a channel noise intensity of a transmission medium for transmitting the third codeword,
• wherein the memory control circuit unit is further configured to determine whether the error level information of the third codeword meets a default condition,
• wherein the error checking and correcting circuit is further configured to decode the third codeword by the first decoding engine in response to that the error level information of the third codeword meets the default condition,
• wherein the error checking and correcting circuit is further configured to decode the third codeword by the second decoding engine in response to that the error level information of the third codeword does not meet the default condition.

A memory control circuit unit adapted to control a rewritable non-volatile memory module comprising a plurality of physical units, the memory control circuit unit comprising:

• a host interface configured to couple to a host system;
• a memory interface configured to couple to the rewritable non-volatile memory module;
• an error checking and correcting circuit comprising a first decoding engine and a second decoding engine;
• and
• a memory management circuit coupled to the host interface, the memory interface, and the error checking and correcting circuit,
• wherein the memory management circuit is configured to issue a first read command sequence to instruct reading a first codeword from a first physical unit among the physical units,
• wherein the memory management circuit is further configured to perform a first parity-check operation on the first codeword to obtain a plurality of first syndromes of the first codeword before the first codeword is decoded,
• wherein the memory management circuit is further configured to accumulate the first syndromes to obtain a first syndrome sum,
• wherein the error checking and correcting circuit is configured to decode the first codeword by the first decoding engine in response to that the first syndrome sum is lower than a default syndrome sum,
• wherein the memory management circuit is further configured to issue a second read command sequence to instruct reading a second codeword from a second physical unit among the physical units,
• wherein the memory management circuit is further configured to perform a second parity-check operation on the second codeword to obtain a plurality of second syndromes of the second codeword before the second codeword is decoded,
• wherein the memory management circuit is further configured to accumulate the second syndromes to obtain a second syndrome sum,
• wherein the error checking and correcting circuit is further configured to decode the second codeword by the second decoding engine in response to that the second syndrome sum is not lower than the default syndrome sum,
• wherein a first power consumption of the first decoding engine for decoding the first codeword is lower than a second power consumption of the second decoding engine for decoding the second codeword,
• wherein the memory management circuit is further configured to issue a third read command sequence to instruct reading a third codeword from a third physical unit among the physical units,
• wherein the memory management circuit is further configured to estimate error level information of the third codeword, wherein the error level information comprises at least one of a programming count of the third physical unit, a reading count of the third physical unit, an erasing count of the third physical unit, a third syndrome sum of the third codeword, a bit error rate of the third codeword, and a channel noise intensity of a transmission medium for transmitting the third codeword,
• wherein the error checking and correcting circuit is further configured to determine whether the error level information of the third codeword meets a default condition,
• wherein the error checking and correcting circuit is further configured to decode the third codeword by the first decoding engine in response to that the error level information of the third codeword meets the default condition,
• wherein the error checking and correcting circuit is further configured to decode the third codeword by the second decoding engine in response to that the error level information of the third codeword does not meet the default condition.