ECC word configuration for system-level ECC compatibility
AssigneeEverspin Technologies, Inc.
InventorsSyed M. Alam, Thomas Andre
Life of this patent
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Abstract
A memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page. The memory device is configurable to perform a first level of error correction on each of the ECC words associated with the page. A system-level error correction circuit is configurable to perform a second level of error correction on the data output by each of the input/output pads during a particular period of time. Each of the one or more input/output pads of the memory device is configurable to provide only one bit of data per ECC word to an external source during an access from an external source.
Claims20
A memory device comprising:
- a memory array storing data associated with a first page, the data associated with the first page organized into a plurality of error correction code (ECC) words;
- a plurality of error correction circuits, each of the plurality of error correction circuits associated with a different ECC word of the plurality of ECC words;
- and
- wherein the memory device is configured to output the data in interleaved sets to a system level error correction circuit, each interleaved set including no more than one bit from each of the plurality of ECC words.
A method comprising:
- receiving a command from an external source to access data stored on a memory device, the data organized on the memory device in multiple error correction code (ECC) words;
- performing a first level error correction on each of the multiple ECC words associated with the data;
- and
- outputting the data to a system level error correction circuit in interleaved sets of bits, each bit of the interleaved set of bits corresponding to a different one of the multiple ECC words, wherein the system level error correction circuit is configured to perform a second level error correction prior to the external source accessing the data.
An electronic device, comprising:
- a system level error correction circuit;
- a memory device including:
- a memory array storing data associated with a first page, the data associated with the first page organized into a plurality of error correction code (ECC) words;
- and
- a plurality of error correction circuits, each of the plurality of error correction circuits associated with a different ECC word of the plurality of ECC words, wherein the memory device is configured to output the data in interleaved sets to the system level error correction circuit, each interleaved set including no more than one bit from each of the plurality of ECC words.
Dependencies are inferred from the claim text.