Test method of delay circuit including delay line

A test method of a delay circuit including a delay line that delays an input signal in accordance with a delay setting signal and performs output of the input signal as a delayed signal, and a logic circuit processes the input signal to the delay line and the delayed signal, the test method comprising:

• inputting the delay setting signal to which a delay amount of the delay line is set, to the delay circuit;
• inputting a test signal of a duty ratio having a large cycle as compared with twice a maximum delay amount of the delay line, to the delay line, as the input signal;
• converting an output of the logic circuit into a voltage value by an integrator;
• measuring the voltage value while changing setting of the delay amount of the delay line;
• and
• checking an operation of the delay circuit from the change in the voltage value and the set delay amount of the delay line,
• the wherein the logic circuit is one of a logical exclusive OR, a logical exclusive-NOR, a logical OR, a logical NOR, a logical AND, and a logical NAND.