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US 10,256,796 B2Granted
Master-slave level shifter array architecture with pre-defined power-up states
AssigneeQUALCOMM Incorporated
InventorsShih-Chieh Hsin, Med Nariman, Jingcheng Zhuang
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Abstract
A master-slave level shifter array includes an asymmetric master level shifter having a predefined output state that produces an enable signal to drive an array of symmetric slave level shifters during a power collapse. As a result, the slave level shifter array has a reliable output state during a power collapse, while also providing wafer area savings due to their small symmetric characteristics.
Claims10
A level shifter array, comprising:
- a master level shifter having a plurality of power states and configured to generate an enable signal in response to a change of power state;
- and
- a plurality of slave level shifters coupled to the master level shifter and configured to receive the enable signal and to generate a default output state of the slave level shifters in response to the enable signal, wherein each of the plurality of slave level shifters comprises:
- an output node carrying a level-shifted version of a slave input signal;
- and
- a NOR gate coupled to receive the level-shifted version of the slave input signal and the enable signal, thereby generating the default output state of the slave level shifters in response to the enable signal.
3 more elements
A level shifter array, comprising:
- a master level shifter having a means for generating an enable signal based upon a pre-defined power-up state;
- and
- one or more slave level shifters having a means for generating a default output state using the enable signal and a level-shifted version of a slave input signal during a power collapse, wherein:
- the means for generating the enable signal comprises an asymmetrical level shifter having a one-sided latch and unbalanced driver;
- the means for generating the default output state comprises a symmetrical level shifter, and
- wherein the master level shifter comprises an unbalanced driver having a first and second pull-down transistor, the first pull-down transistor being larger in size than the second pull-down transistor.
3 more elements
Dependencies are inferred from the claim text.