Multiphase interleaved pulse frequency modulation for a DC-DC converter

A method, comprising:

• comparing a voltage level of an output of a regulator circuit to a reference voltage level to generate a target voltage level;
• selecting a particular feedback signal of a plurality of feedback signals and a corresponding pulse control circuit of a plurality of pulse control circuits, wherein each of the plurality of feedback signals is coupled to a respective input node of a respective one of the plurality of pulse control circuits;
• adding a respective offset to a voltage level of each of the plurality of feedback signals except the particular feedback signal;
• based on a comparison of the voltage level of the particular feedback signal to the target voltage level, sourcing, by the corresponding pulse control circuit, a current pulse to a load circuit coupled to the output of the regulator circuit;
• and
• in response to determining a period of time has elapsed, adding a respective offset to the voltage level of the particular feedback signal, and removing the respective offset from a voltage level of a newly selected feedback signal coupled to a newly selected pulse control circuit of the plurality of pulse control circuits.

A non-transitory computer-readable storage medium having design information stored thereon, wherein the design information specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the hardware integrated circuit according to the design information, wherein the design information specifies that the hardware integrated circuit comprises:

• a plurality of pulse control circuits, wherein a given pulse control circuit of the plurality of pulse control circuits is configured to source a current pulse to an output power signal based on a comparison of a particular feedback signal of a plurality of feedback signals and a target voltage signal;
• a control circuit configured to:
• offset a voltage level of each feedback signal of a first subset of the plurality of feedback signals, wherein the first subset excludes a first feedback signal;
• and
• in response to a determination that a period of time has ended, offset a voltage level of each feedback signal of a second subset of the plurality of feedback signals, wherein the second subset includes the first feedback signal and excludes a second feedback signal.