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US 10,256,426 B2Granted
Thin-film transistor array panel and manufacturing method thereof
AssigneeShenzhen China Star Optoelectronocs Technolo9Gy Co., Ltd.
InventorXiaowen Lv
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Abstract
A thin-film transistor array panel and a manufacturing method thereof are disclosed. The thin-film transistor array panel has a polysilicon layer including a first region, a second region and a third region. The second region includes a fourth region, a fifth region and a sixth region. The third region includes a seventh region, an eighth region and ninth region. The sixth, the fourth, the ninth and the seventh regions are doped with first, second, third and fourth ions, respectively. In a thin-film transistor of the thin-film transistor array panel, a gate electrode, a source electrode and a drain electrode thereof correspond to the first, the sixth and the ninth regions, respectively. The device is able to reduce leakage current in the thin-film transistor.
Claims11
A thin-film transistor array panel comprising:
- a substrate;
- a buffer layer;
- a first insulating layer;
- a plurality of thin-film transistors, each of which includes:
- a polysilicon layer disposed between the buffer layer and the first insulating layer;
- a gate electrode mounted on the first insulating layer;
- a source electrode;
- and
- a drain electrode;
- a second insulating layer;
- a display device layer;
- wherein
- the polysilicon layer includes a first region, a second region and a third region;
- and the first region is disposed between the second region and the third region;
- the second region includes a fourth region, a fifth region and a sixth region;
- the fifth region is disposed between the fourth region and the sixth region;
- the fourth region is disposed between the first region and the fifth region;
- the sixth region is doped with first ions;
- the fourth region is doped with second ions;
- the third region includes a seven region, an eighth region and a ninth region;
- the eighth region is disposed between the seventh region and the ninth region;
- the seventh region is disposed between the first region and the eighth region;
- the ninth region is doped with third ions;
- the seventh region is doped with fourth ions;
- the position of the gate electrode corresponds to the first region;
- the source electrode is in contact with a portion of the polysilicon layer in the sixth region;
- the drain electrode is in contact with a portion of the polysilicon layer in the ninth region;
- a portion of the polysilicon layer in the second region and/or a portion of the polysilicon layer in the third region are used to reduce leakage current of the thin-film transistor;
- a portion of the polysilicon layer in the fifth region separates a portion of the polysilicon layer in the sixth region and a portion of the polysilicon layer in the fourth region;
- a portion of the polysilicon layer in the eighth region separates a portion of the polysilicon layer in the seventh region and a portion of the polysilicon layer in the ninth region;
- wherein
- the first ions have a third gradient doping concentration in the portion of the polysilicon layer in the sixth region;
- the second ions have a fourth gradient doping concentration in the portion of the polysilicon layer in the fourth region;
- the third ions have a fifth gradient doping concentration in the portion of the polysilicon layer in the ninth region;
- the fourth ions have a sixth gradient doping concentration in the portion of the polysilicon layer in the seventh region.
32 more elements
A thin-film transistor array panel comprising:
- a substrate;
- a buffer layer;
- a first insulating layer;
- a plurality of thin-film transistors, each of which includes:
- a polysilicon layer disposed between the buffer layer and the first insulating layer;
- a gate electrode mounted on the first insulating layer,
- a source electrode;
- and
- a drain electrode;
- a second insulating layer;
- a display device layer;
- wherein
- the polysilicon layer includes a first region, a second region and a third region;
- and the first region is disposed between the second region and the third region;
- the second region includes a fourth region, a fifth region and a sixth region;
- the fifth region is disposed between the fourth region and the sixth region;
- the fourth region is disposed between the first region and the fifth region;
- the sixth region is doped with first ions;
- the fourth region is doped with second ions;
- the third region includes a seven region, an eighth region and a ninth region;
- the eighth region is disposed between the seventh region and the ninth region;
- the seventh region is disposed between the first region and the eighth region;
- the ninth region is doped with third ions;
- the seventh region is doped with fourth ions;
- the source electrode is in contact with a portion of the polysilicon layer in the sixth region;
- the drain electrode is in contact with a portion of the polysilicon layer in the ninth region;
- wherein
- the first ions have a third gradient doping concentration in the portion of the polysilicon layer in the sixth region;
- the second ions have a fourth gradient doping concentration in the portion of the polysilicon layer in the fourth region;
- the third ions have a fifth gradient doping concentration in the portion of the polysilicon layer in the ninth region;
- the fourth ions have a sixth gradient doping concentration in the portion of the polysilicon layer in the seventh region.
28 more elements
Dependencies are inferred from the claim text.