Memory device with multiple interconnect lines
AssigneeToshiba Memory Corporation
InventorsHarumi Seki, Takayuki Ishikawa, Masumi Saitoh
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AssigneeToshiba Memory Corporation
InventorsHarumi Seki, Takayuki Ishikawa, Masumi Saitoh
Estimating the term…
According to one embodiment, a memory device includes a first interconnect, a second interconnect, a first layer, a second layer. The first interconnect includes a first region and a second region. The first region extends in a first direction and includes a first metallic element. The second region extends in the first direction and includes the first metallic element and nitrogen. The second interconnect extends in a second direction crossing the first direction. A portion of the second region is positioned between the second interconnect and a portion of the first region. The first layer is provided between the second interconnect and the portion of the second region. The second layer is provided between the first layer and the second interconnect. The second layer includes at least one of silicon or a second oxide. The silicon is monocrystalline, polycrystalline, or amorphous.
A memory device, comprising:
A memory device, comprising:
Dependencies are inferred from the claim text.