Structure and method to reduce shorting and process degradation in stt-MRAM devices

#The present invention relates to spin-transfer torque magnetoresistive random access memory (STT-MRAM devices), and more specifically, to stack structures and etch processes in STT-MRAM devices.

#STT-MRAM devices have some benefits over semiconductor-based memories, such as dynamic random-access memory (DRAM) and static random-access memory (SRAM). However, in order to compete with DRAM and SRAM, the STT-MRAM devices are integrated into the wiring layers of standard silicon logic and memory chips.

#STT-MRAM device is a type of solid state, non-volatile memory that uses tunneling magnetoresistance (TMR or MR) to store information. MRAM includes an electrically connected array of magnetoresistive memory elements, referred to as magnetic tunnel junctions (MTJs). Each MTJ includes a free layer and fixed/reference layer that each includes a magnetic material layer. A non-magnetic insulating tunnel barrier separates the free and fixed/reference layers. The free layer and the reference layer are magnetically de-coupled by the tunnel barrier. The free layer has a variable magnetization direction, and the reference layer has an invariable magnetization direction.

#The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

#FIGS. 1A-1C illustrate methods of making MRAM devices that result in metal redeposition along sidewalls of the tunnel barrier; in which:

#FIG. 1A is a cross-sectional side view of a patterned hard mask disposed on a MTJ stack;

#One challenge of integrating STT-MRAM devices into wiring layers of silicon logic and memory chips is subtractive etching of the magnetic stack from a blanket film. Specialized reactive ion etches (RIE) and inert ion beam etches (IBE) may be used. However, RIE processes for etching MRAM may cause device degradation. Although IBE processes may not induce as much magnetic damage, they may cause metal redeposition (described in FIGS. 1A-1C below) that can induce electrical shorting across the tunnel barrier layer. Shorting across the tunnel barrier layer may reduce device yields. Metal redeposition can be removed by oxidizing the redeposited metal to make it insulating, but the oxidation process may also cause device degradation.

#For example, FIGS. 1A-1C illustrate methods of making MRAM devices that result in metal redeposition along sidewalls of the tunnel barrier layer 103. FIG. 1A is a cross-sectional side view of a patterned hard mask 110 disposed on a MTJ stack 105. The MTJ stack 105 includes a reference layer 102, a tunnel barrier layer 103, and a free layer 104. The reference layer 102 and the free layer 104 include conductive, magnetic metals or metal alloys. The MTJ stack 105 is disposed on a contact electrode 101 (bottom contact). A hard mask 110 is disposed on the MTJ stack 105. The hard mask 110 is then patterned.

#FIG. 1B is a cross-sectional side view after transferring the pattern of the hard mask 110 into the free layer 104 and the tunnel barrier layer 103 of the MTJ stack 105. The free layer 104 and the tunnel barrier layer 103 are etched, by, for example, a RIE or IBE process. During the etch process, the magnetic material of the free layer 104 is redeposited along the sidewalls of the free layer 104, the tunnel barrier layer 103, and/or the hard mask 110.