Structures for nitride vertical transistors
AssigneeMassachusetts Institute of Technology
InventorsMin Sun, Tomas Apostol Palacios
Life of this patent
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Abstract
A vertical semiconductor transistor and a method of forming the same. A vertical semiconductor transistor has at least one semiconductor region, a source, and at least one gate region. The at least one semiconductor region includes a III-nitride semiconductor material. The source is formed over the at least one semiconductor region. The at least one gate region is formed around at least a portion of the at least one semiconductor region.
Claims23
A vertical semiconductor transistor comprising:
- at least one semiconductor region including a first semiconductor region and a second semiconductor region having the same type of doping, wherein the at least one semiconductor region includes a III-nitride semiconductor material and the first semiconductor region is adjacent to the second semiconductor region, and wherein the first semiconductor region has a higher dopant concentration than the second semiconductor region;
- a source formed over the at least one semiconductor region;
- at least one gate region formed around at least a portion of the first semiconductor region, wherein the at least one gate region includes a metal;
- and
- a dielectric layer between the at least one semiconductor region and the at least one gate region.
A vertical semiconductor transistor comprising:
- at least one semiconductor region including a first region and a second region, wherein the at least one semiconductor region includes a III-nitride semiconductor material, and wherein the first region and the second region have different types of doping;
- a source formed over the first region;
- at least one gate region formed around at least a portion of only the second region, wherein the at least one gate region includes a metal;
- and
- an oxide layer between the at least one semiconductor region and the at least one gate region.
A method of forming a vertical semiconductor transistor, the method comprising:
- forming at least one semiconductor region including a first semiconductor region and a second semiconductor region having the same type of doping, wherein the at least one semiconductor region includes a III-nitride semiconductor material and the first semiconductor region is adjacent to the second semiconductor region, and wherein the first semiconductor region has a higher dopant concentration than the second semiconductor region;
- forming a source over the at least one semiconductor region;
- forming at least one gate region around at least a portion of the first semiconductor region, wherein the at least one gate region includes a metal;
- and
- forming a dielectric layer between the at least one semiconductor region and the at least one gate region.
A method of forming a vertical semiconductor transistor, the method comprising:
- forming at least one semiconductor region including a first region and a second region, wherein the at least one semiconductor region includes a III-nitride semiconductor material, and wherein the first region and the second region have different types of doping;
- forming a source over the first region;
- forming at least one gate region around at least a portion of only the second region, wherein the at least one gate region includes a metal;
- and
- forming an oxide layer between the at least one semiconductor region and the at least one gate region.
Dependencies are inferred from the claim text.