Semi-floating gate FET
AssigneeSTMicroelectronics S.r.l.
InventorsQing Liu, John H. Zhang
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AssigneeSTMicroelectronics S.r.l.
InventorsQing Liu, John H. Zhang
Estimating the term…
A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.
A method of making a vertical semi-floating gate transistor, the method comprising:
A method of making a vertical semi-floating gate transistor, the method comprising:
A method, comprising:
A method, comprising:
Dependencies are inferred from the claim text.