Semiconductor device and method for manufacturing semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsYuta Endo, Hideomi Suzawa, Kazuya Hanaoka, Shinya Sasagawa, Satoru Okamoto
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AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsYuta Endo, Hideomi Suzawa, Kazuya Hanaoka, Shinya Sasagawa, Satoru Okamoto
Estimating the term…
A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.
A method for manufacturing a semiconductor device, comprising the steps of:
A method for manufacturing a semiconductor device, comprising the steps of:
Dependencies are inferred from the claim text.