Methods of manufacturing fin field effect transistors (FinFETs) comprising reduced gate thicknesses overlying deep trenches

A method of manufacturing an integrated circuit (IC) device, the method comprising:

• forming an insulating layer on a substrate that includes a device region having a fin-type active region and a deep trench region that is configured to define the device region, the insulating layer extending over the device region and the deep trench region and exposing the fin-type active region;
• forming a conductive line that extends on the insulating layer and the fin-type active region while intersecting the fin-type active region and that covers the device region and the deep trench region;
• and
• forming a gate line by removing a portion of the conductive line that is on the deep trench region by a predetermined thickness from an upper surface of the conductive line so that the gate line includes a first upper surface having a first level in the device region and a second upper surface having a second level that is closer to the substrate than the first level, in the deep trench region, wherein forming the conductive line comprises:
• forming a dummy gate line on the insulating layer and the fin-type active region;
• forming an insulating spacer covering both sidewalls of the dummy gate line;
• forming a gate space that is defined by the insulating spacer, by removing the dummy gate line;
• and
• forming the conductive line having a flattened upper surface in the gate space.

A method of manufacturing an integrated circuit (IC) device, the method comprising:

• forming an insulating layer on a substrate, the substrate including a device region having a fin-type active region and an isolation region configured to define the device region, the insulating layer extending over the device region and the isolation region and exposing the fin-type active region;
• forming a conductive line that extends on the insulating layer and the fin-type active region while intersecting the fin-type active region and that covers the device region and the isolation region;
• and
• removing a portion of the conductive line overlying the isolation region to create a reduced thickness section in the conductive line over the isolation region, wherein a vertical thickness of the reduced thickness section is smaller than a vertical thickness of the conductive line overlying the device region.