Insulated gate turn-off device having low capacitance and low saturation current

An insulated gate turn-off (IGTO) device formed as a die comprising:

• a first semiconductor layer of a first conductivity type coupled to a first electrode;
• a second semiconductor layer of a second conductivity type overlying the first semiconductor layer;
• a third semiconductor layer of the first conductivity type overlying at least a portion of the second semiconductor layer;
• an array of cells comprising:
• a plurality of insulated gates within trenches not extending through the third semiconductor layer, the insulated gates being electrically connected together, the insulated gates forming a conductive mesh having first openings and second openings when viewed from a top of the device;
• a first semiconductor region of the second conductivity type overlying the third semiconductor layer and adjacent to at least one side of each of the insulated gates, the first semiconductor region being connected to a second electrode, the second electrode being on a first side of the die, and the first electrode being on a second side of the die,
• wherein the cells conduct a current when the IGTO device is forward biased and the insulated gates are biased above a threshold voltage,
• wherein at least a first subset of the insulated gates has the first semiconductor region adjacent to the insulated gates in the first subset only within the first openings of the mesh to form active cells within the first openings that conduct current, and
• wherein first subset of the insulated gates have the first semiconductor region not adjacent to the insulated gates in the first subset within the second openings of the mesh to form passive cells within the second openings that do not conduct current.