Semiconductor device including enhanced low-k spacer
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Zuoguang Liu, Chun W. Yeung
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Abstract
A semiconductor device includes a semiconductor substrate including a channel region and a source/drain region, and an electrically conductive gate on an upper surface of the channel region. An electrically conductive source/drain contact is on an upper surface of the source/drain region. The semiconductor device further includes enhanced low-k spacer on an upper surface of the substrate and interposed between the electrically conductive gate and the electrically conductive source/drain contact. The enhanced low-k spacer includes a stacked arrangement of a dielectric material and a ferroelectric material.
Claims20
A semiconductor device comprising:
- a semiconductor substrate including a channel region and a source/drain region;
- an electrically conductive gate on an upper surface of the channel region;
- an electrically conductive source/drain contact on an upper surface of the source/drain region;
- and
- an enhanced low-k spacer on an upper surface of the substrate and interposed between the electrically conductive gate and the electrically conductive source/drain contact;
- wherein the enhanced low-k spacer includes a stacked arrangement of a dielectric material and a ferroelectric material.
A field effect transistor (FET) including enhanced low-k spacers, the FET comprising:
- a semiconductor substrate including a channel region interposed between a first source/drain region and a second source/drain region;
- an electrically conductive gate on an upper surface of the channel region;
- a first electrically conductive source/drain contact on an upper surface of the first source/drain region, and a second electrically conductive source/drain contact on an upper surface of the second source/drain region;
- a first stacked arrangement of a dielectric material and a ferroelectric material interposed between the first electrically conductive source/drain contact and the electrically conductive gate that defines a first enhanced low-k spacer;
- and
- a second stacked arrangement of a dielectric material and a ferroelectric material interposed between the second electrically conductive source/drain contact and the electrically conductive gate that defines a second enhanced low-k spacer.
A method of fabricating a semiconductor device including an enhanced low-k spacer, the method comprising:
- forming a semiconductor substrate including a channel region and a source/drain region;
- forming an electrically conductive gate on an upper surface of the channel region;
- forming an electrically conductive source/drain contact on an upper surface of the source/drain region;
- and
- stacking together a dielectric material and a ferroelectric material between the electrically conductive gate and the electrically conductive source/drain contact to form the enhanced low-k spacer.
Dependencies are inferred from the claim text.