Vertical transistor gated diode
AssigneeInternational Business Machines Corporation
InventorsKarthik Balakrishnan, Alexander Reznicek
Life of this patent
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Abstract
After forming a trench extending through a sacrificial gate layer to expose a surface of a doped bottom semiconductor layer, a diode including a first doped semiconductor segment and a second doped semiconductor segment having a different conductivity type than the first doped semiconductor segment is formed within the trench. The sacrificial gate layer that laterally surrounds the first doped semiconductor segment and the second doped semiconductor segment is subsequently replaced with a gate structure to form a gated diode.
Claims8
A method of forming a semiconductor structure comprising:
- forming a first doped semiconductor segment of a first conductivity type in a lower portion of a trench that extends through a material stack located on a doped bottom semiconductor layer of the first conductivity type, wherein the material stack comprises, from bottom to top, a bottom spacer layer, a sacrificial gate layer, and a dielectric capping layer, wherein a protective layer is formed on sidewalls of the sacrificial gate layer that are exposed by the trench prior to the forming of the first doped semiconductor segment;
- forming a second doped semiconductor segment of a second conductivity type on the first doped semiconductor segment within the trench, wherein the second conductivity type is opposite from the first conductivity type;
- removing the dielectric capping layer to exposing a top portion of the second doped semiconductor segment;
- forming a doped top semiconductor region of the second conductivity type laterally surrounding the top portion of the second doped semiconductor segment;
- forming a sidewall spacer on sidewalls of the doped top semiconductor region;
- removing the sacrificial gate layer;
- and
- forming a gate structure laterally surrounding an upper portion of the first doped semiconductor segment and a lower portion of the second doped semiconductor segment previously covered by the sacrificial gate layer, wherein the protective layer is removed prior to the forming of the gate structure.
A method of forming a semiconductor structure comprising:
- forming a first doped semiconductor segment of a first conductivity type in a lower portion of a trench that extends through a material stack located on a doped bottom semiconductor layer of the first conductivity type, wherein the material stack comprises, from bottom to top, a bottom spacer layer, a sacrificial gate layer, and a dielectric capping layer;
- forming a second doped semiconductor segment of a second conductivity type on the first doped semiconductor segment within the trench, wherein the second conductivity type is opposite from the first conductivity type;
- forming a dielectric cap on the second doped semiconductor segment within the trench, wherein the dielectric cap has a top surface coplanar with a top surface of the dielectric capping layer, and the sidewall spacer is present on sidewalls of the dielectric cap;
- removing the dielectric capping layer to exposing a top portion of the second doped semiconductor segment;
- forming a doped top semiconductor region of the second conductivity type laterally surrounding the top portion of the second doped semiconductor segment;
- forming a sidewall spacer on sidewalls of the doped top semiconductor region;
- removing the sacrificial gate layer;
- and
- forming a gate structure laterally surrounding an upper portion of the first doped semiconductor segment and a lower portion of the second doped semiconductor segment previously covered by the sacrificial gate layer.
Dependencies are inferred from the claim text.