Semiconductor structure with a gap between conductor features and fabrication method thereof
AssigneesUnited Microelectronics Corp., Fujian Jinhua Integrated Circuit Co., Ltd.
InventorsFeng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Yi-Ching Chang
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Abstract
A semiconductor structure includes a contact plug located on a barrier layer in a contact hole; a first conductive feature integrally formed with the contact plug on the barrier layer; a second conductive feature disposed on the interlayer dielectric layer; and a gap between the first and second conductive features. The gap includes a vertical trench recessed into the interlayer dielectric layer, and a discontinuity in the barrier layer. The discontinuity extends below the second conductive feature to form an undercut structure.
Claims21
A semiconductor structure, comprising:
- a substrate having thereon a conductive region;
- an interlayer dielectric (ILD) layer covering the substrate;
- a contact hole in the ILD layer, wherein the contact hole partially exposes the conductive region;
- a barrier layer conformally lining interior surface of the contact hole and a top surface of the ILD layer;
- a contact plug in the contact hole and on the barrier layer;
- a first conductor feature integrally constructed on the contact plug;
- a second conductor feature disposed on the top surface of the ILD layer, wherein the second conductor feature is in close proximity to the first conductor feature;
- and
- a gap between the first conductor feature and the second conductor feature, wherein the gap comprises a vertical trench recessed into the ILD layer and a discontinuity in the barrier layer, wherein the discontinuity creates an undercut directly under the second conductor feature, wherein the first conductor feature and the second conductor feature are coplanar and are formed from a same level of metal interconnection.
A method for fabricating a semiconductor structure, comprising:
- providing a substrate having thereon a conductive region and an interlayer dielectric (ILD) layer covering the substrate and the conductive region;
- forming a contact hole in the ILD layer, wherein the contact hole partially exposes the conductive region;
- forming a barrier layer conformally lining interior surface of the contact hole and a top surface of the ILD layer;
- depositing a conductive layer on the barrier layer, wherein the contact hole is filled with the conductive layer so as to form a contact plug therein;
- performing a lithographic process and an anisotropic process to etch the conductive layer, the barrier layer and the ILD layer so as to form a first conductor feature integrally constructed on the contact plug and a second conductor feature disposed on the top surface of the ILD layer, wherein the second conductor feature is in close proximity to the first conductor feature;
- performing a selective etching process to selectively etch the barrier layer thereby forming a gap between the first conductor feature and the second conductor feature, wherein the gap comprises a vertical trench recessed into the ILD layer and a discontinuity in the barrier layer, wherein the discontinuity creates an undercut directly under the second conductor feature;
- depositing a gap fill material layer on the first and second conductor features and into the gap;
- and
- polishing the gap fill material layer such that a top surface of the gap fill material layer is flush with a top surface of the first conductor feature and a top surface of the second conductor feature.
Dependencies are inferred from the claim text.