Split-gate flash memory cell having a floating gate situated in a concave trench in a semiconductor substrate

A split-gate flash memory cell, comprising:

• a semiconductor substrate having a source region and a drain region, wherein the source region and the drain region are separated by a channel region;
• a concave trench in the semiconductor substrate;
• a first dielectric layer on the semiconductor substrate, wherein the first dielectric layer has a first portion that is outside the concave trench and on a top surface of the semiconductor substrate, and the first dielectric layer has a second portion that is inside the concave trench and lines the concave trench;
• a floating gate situated in the concave trench on the second portion of the first dielectric layer;
• a dielectric material on the floating gate;
• a second dielectric layer on the first dielectric layer, the floating gate, and the dielectric material, wherein the first portion of the first dielectric layer is between the second dielectric layer and the top surface of the semiconductor substrate;
• and
• a control gate on the second dielectric layer.