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US 10,256,302 B2Granted
Vertical transistor with air-gap spacer
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Tak H. Ning
Life of this patent
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Abstract
A vertical transistor has a first air-gap spacer between a gate and a bottom source/drain region, and a second air-gap spacer between the gate and the contact to the bottom source/drain region. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.
Claims16
A vertical transistor comprising:
- a fin or nanowire extending upward from a surface of a semiconductor substrate;
- a gate electrode located entirely adjacent to each sidewall of the fin or nanowire;
- a bottom source/drain contact adjacent to the gate electrode;
- a dielectric spacer disposed between the gate electrode and the bottom source/drain contact, wherein the dielectric spacer comprises a vertical air-gap embedded in a dielectric material;
- a bottom source/drain region having a topmost surface directly contacting a bottommost surface of the fin or nanowire;
- and
- a top source/drain region having a bottommost surface directly contacting a topmost surface of the fin or nanowire.
4 more elements
Dependencies are inferred from the claim text.