Vertical gallium nitride power field-effect transistor with a field plate structure
AssigneeQorvo US, Inc.
InventorsSubrahmanyam V. Pilla, Tso-Min Chou
Life of this patent
Estimating the term…
Abstract
The present disclosure relates to a vertical gallium-nitride (GaN) power field-effect transistor (FET) with a field plate structure. The vertical GaN power FET includes a conductive substrate, a drift region, a field plate structure, a channel region with tapered side walls, a gate dielectric region, a gate contact, a drain contact and source contacts. The field plate structure includes a lower layer formed of pi p-type graded AlGaN and a upper layer formed of p-type GaN. The field plate structure utilizes the charge separation at the interface between the lower layer and the upper layer to achieve high breakdown voltage.
Claims20
A gallium-nitride (GaN) power field-effect transistor (FET) comprising:
- a conductive substrate;
- a drift region residing over a top surface of the conductive substrate and having a recess;
- a field plate structure residing over the drift region and comprising a lower layer formed of graded aluminum gallium nitride (AlGaN) over the drift region, and an upper layer formed of non-graded GaN and essentially free of aluminum content over the lower layer, wherein:
- the lower layer and the upper layer are doped with a same polarity of dopants;
- the lower layer and the upper layer have different dopant densities;
- and
- a percentage of aluminum in the graded AlGaN of the lower layer decreases from no more than 33% to 0% from a bottom to a top of the lower layer;
- a channel region extending vertically through the field plate structure and into the recess, wherein the channel region is formed of GaN and directly surrounded by the upper layer and the lower layer of the field plate structure;
- a gate dielectric region over the channel region;
- a gate contact over the gate dielectric region;
- source contacts over the upper layer of the field plate structure;
- a drain contact over a bottom surface of the conductive substrate;
- and
- ohmic contact regions and source contact regions within the upper layer of the field plate structure, wherein the source contact regions and the upper layer of the field plate structure are doped with different polarities of dopants.
A gallium-nitride (GaN) power field-effect transistor (FET) comprising:
- a conductive substrate;
- a drift region residing over a top surface of the conductive substrate and having a recess;
- a field plate structure residing over the drift region and comprising a lower layer formed of graded indium gallium nitride (InGaN) over the drift region, and an upper layer formed of non-graded GaN and essentially free of indium content over the lower layer, wherein:
- the lower layer and the upper layer are doped with a same polarity of dopants;
- the lower layer and the upper layer have different dopant densities;
- and
- a percentage of indium in the InGaN of the lower layer decreases from no more than 33% to 0% from a bottom to a top of the lower layer;
- a channel region extending vertically through the field plate structure and into the recess, wherein the channel region is formed of GaN and directly surrounded by the upper layer and the lower layer of the field plate structure;
- a gate dielectric region over the channel region;
- a gate contact over the gate dielectric region;
- source contacts over the upper layer of the field plate structure;
- a drain contact over a bottom surface of the conductive substrate;
- and ohmic contact regions and source contact regions within the upper layer of the field plate structure, wherein the source contact regions and the upper layer of the field plate structure are doped with different polarities of dopants.
Dependencies are inferred from the claim text.