Resistive memory device containing etch stop structures for vertical bit line formation and method of making thereof

A resistive memory device, comprising:

• a two-dimensional array of vertical field effect transistors located over a substrate and including a two-dimensional array of semiconductor pillars laterally spaced among one another by dielectric rail structures that extend along in a first horizontal direction, and laterally spaced among one another in the second horizontal direction by dielectric pillar structures;
• an etch stop dielectric material layer overlying top surfaces of the dielectric rail structures and the dielectric pillar structures and including openings in areas that overlie the two-dimensional array of semiconductor pillars;
• an array of metal nitride portions located within the openings in the etch stop dielectric material layer and electrically connected to top surfaces of each semiconductor pillar within the two-dimensional array of semiconductor pillars;
• a two-dimensional array of vertical bit lines electrically connected to the metallic nitride portions;
• alternating layer stacks located between neighboring rows of the vertical bit lines and overlying the etch stop dielectric material layer, wherein each of the alternating layer stacks comprises a vertically alternating sequence of insulating strips and electrically conductive word line strips;
• and
• a vertical stack of resistive memory elements located between each of the vertical bit lines and alternating layer stacks to provide a three-dimensional resistive memory element array.