Three-dimensional memory device containing structurally reinforced pedestal channel portions and methods of making the same

A three-dimensional memory device comprising:

• an alternating stack of insulating layers and electrically conductive layers located over a substrate;
• a memory opening extending through the alternating stack;
• a semiconductor pedestal channel portion located at a bottom portion of the memory opening;
• and
• a memory stack structure located in the memory opening and contacting a top surface of the pedestal channel portion, wherein the memory stack structure comprises a memory film and a vertical semiconductor channel located inside the memory film,
• wherein:
• a bottommost insulating layer among the insulating layers comprises a first silicon oxide material, and at least some of the insulating layers other than the bottommost insulating layer comprise a second silicon oxide material having a greater density than the first silicon oxide material:
• the pedestal channel portion has an upper pedestal lateral extent, which is a maximum lateral extent of an entire portion of the pedestal channel portion located above a first horizontal plane including a bottom surface of the bottommost insulating layer among the insulating layers;
• and
• an upper memory stack structure lateral extent, which is a maximum lateral extent of an entire portion of the memory stack structure located above a horizontal plane including a top surface of the bottommost insulating layer, is less than the upper pedestal lateral extent.

A three-dimensional memory device comprising:

• an alternating stack of insulating layers and electrically conductive layers located over a substrate;
• a memory opening extending through the alternating stack;
• a semiconductor pedestal channel portion located at a bottom portion of the memory opening;
• a memory stack structure located in the memory opening and contacting a top surface of the pedestal channel portion, wherein the memory stack structure comprises a memory film and a vertical semiconductor channel located inside the memory film;
• and
• an annular silicon oxide spacer laterally surrounding the pedestal channel portion and located between the pedestal channel portion and a bottommost electrically conductive layer among the electrically conductive layers;
• wherein:
• a bottommost insulating layer among the insulating layers comprises a first silicon oxide material, and at least some of the insulating layers other than the bottommost insulating layer comprise a second silicon oxide material having a greater density than the first silicon oxide material;
• the electrically conductive layers comprise word lines, source select gate electrode and drain select gate electrode of a NAND memory device;
• the bottommost electrically conductive layer comprises the source select gate electrode;
• the source select gate electrode is more distal from the vertical axis than the word lines;
• and
• the annular silicon oxide spacer comprises a gate dielectric of a source select transistor of the NAND memory device.

A three-dimensional memory device comprising:

• an alternating stack of insulating layers and electrically conductive layers located over a substrate;
• a memory opening extending through the alternating stack;
• a semiconductor pedestal channel portion located at a bottom portion of the memory opening;
• and
• a memory stack structure located in the memory opening and contacting a top surface of the pedestal channel portion, wherein the memory stack structure comprises a memory film and a vertical semiconductor channel located inside the memory film,
• wherein:
• a bottommost insulating layer among the insulating layers comprises a first silicon oxide material, and at least some of the insulating layers other than the bottommost insulating layer comprise a second silicon oxide material having a greater density than the first silicon oxide material;
• the memory opening has a sidewall that has a laterally-undulating vertical cross-sectional profile;
• each electrically conductive layer other than a bottommost electrically conductive layer in the alternating stack is more proximal to the vertical axis than each insulating layer other than the bottommost insulating layer in the alternating stack;
• the bottommost insulating layer is more distal from the vertical axis than each electrically conductive layer other than the bottommost electrically conductive layer;
• and
• the bottommost electrically conductive layer is more distal from the vertical axis than the bottommost insulating layer.

A method of forming a three-dimensional memory device, comprising:

• forming an alternating stack of insulating layers and sacrificial material layers over a substrate, wherein a bottommost sacrificial material layer comprises a first sacrificial material, at least some of remaining sacrificial material layers other than the bottommost sacrificial material layer comprise a second sacrificial material that is different from the first sacrificial material, a bottommost insulating layer comprises a first insulating material, and at least some of remaining insulating layers other than the bottommost insulating layer comprise a second insulating material that is different from the first insulating material;
• forming a memory opening through the alternating stack;
• laterally recessing the bottommost insulating layer and the bottommost sacrificial material layer selective to the remaining sacrificial material layers and the remaining insulating layers around the memory opening;
• forming a pedestal channel portion at a bottom portion of the memory opening at a level of the bottommost sacrificial material layer by a selective semiconductor deposition process;
• forming a memory stack structure in a remaining volume of the memory opening and directly on the pedestal channel portion, wherein the memory stack structure comprises a memory film and a vertical semiconductor channel;
• and
• replacing the sacrificial material layers with electrically conductive layers.