Three dimensional semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsKihyun Kim, Chadong Yeo
Life of this patent
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Abstract
A three-dimensional semiconductor memory device is provided. A stacked structure is formed on a substrate. The stacked structure includes conductive patterns vertically stacked on the substrate. A selection structure including selection conductive patterns is stacked on the stacked structure. A channel structure penetrates the selection structure and the stacked structure to connect to the substrate. An upper interconnection line crosses the selection structure. A conductive pad is disposed on the channel structure to electrically connect the upper interconnection line to the channel structure. A bottom surface of the conductive pad is positioned below a top surface of the uppermost selection conductive pattern of the selection conductive patterns.
Claims15
A three-dimensional semiconductor memory device, comprising:
- a stacked structure including a plurality of conductive patterns vertically stacked on a substrate;
- a selection structure including first, second, and third selection conductive patterns sequentially stacked on the stacked structure;
- a channel structure penetrating the selection structure and the stacked structure to connect to the substrate;
- an upper interconnection line crossing the selection structure;
- and
- a conductive pad disposed on the channel structure to electrically connect the upper interconnection line to the channel structure,
- wherein a bottom surface of the conductive pad is positioned between top and bottom surfaces of the third selection conductive pattern,
- wherein the conductive pad has impurities of a first conductivity type, and the channel structure comprises a channel impurity region having impurities of a second conductivity type different from the first conductivity type and positioned adjacent to the first and second selection conductive patterns, and
- wherein the channel impurity region is spaced apart from the bottom surface of the conductive pad.
A three-dimensional semiconductor memory device, comprising:
- a substrate;
- a vertical channel formed on the substrate;
- a conductive pad formed on the vertical channel, wherein the conductive pad includes impurities of a first conductivity type;
- a bit line formed on the conductive pad, wherein the bit line is electrically coupled to the conductive pad;
- a plurality of word lines vertically formed on the substrate which is adjacent to the vertical channel;
- and
- first, second, and third selection conductive patterns sequentially stacked on the plurality of word lines,
- wherein the vertical channel includes a channel impurity region and an offset region, wherein the offset region is interposed between the conductive pad and the channel impurity region, and wherein the channel impurity region has impurities of a second conductivity type different from the first conductivity type,
- wherein the channel impurity region is adjacent the first and second selection conductive patterns, and
- wherein an impurity concentration of the channel impurity region is maximum at a position between the first and the second selection conductive patterns.
Dependencies are inferred from the claim text.