Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof

A semiconductor structure comprising:

• a memory-level assembly located over a semiconductor substrate and comprising an alternating stack of insulating layers and spacer dielectric layers having portions thereof replaced with electrically conductive layers, wherein a respective spacer dielectric layer and a respective electrically conductive layer are laterally adjoined to each other, and wherein each spacer dielectric layer within the alternating stack other than a bottommost one of the spacer dielectric layers within the alternating stack has a greater lateral extent than any overlying one of the spacer dielectric layers within the alternating stack;
• a retro-stepped dielectric material portion overlying, and contacting, stepped surfaces of the alternating stack;
• memory stack structures vertically extending through the alternating stack, wherein each of the memory stack structures comprises:
• a vertical semiconductor channel;
• and
• a memory film comprising a tunneling dielectric and charge storage regions;
• and
• at least one through-memory-level via structure consisting of at least one conductive material and vertically extending through the retro-stepped dielectric material portion, a respective subset of the spacer dielectric layers within the alternating stack, and a respective subset of the insulating layers within the alternating stack, and is laterally spaced from each of the electrically conductive layers within the alternating stack.