Semiconductor structure, static random access memory, and fabrication method thereof

A method for fabricating a semiconductor structure, comprising:

• providing a base substrate, including a substrate and a plurality of discrete fins on the substrate, wherein the substrate includes a pull-up transistor region and a pull-down transistor region adjacent to the pull-up transistor region;
• performing a pull-down threshold adjustment implantation treatment on the base substrate corresponding to the second pull-down doped region;
• forming a gate structure, across a length portion of each fin, covering top and sidewall surfaces of each fin, and on each fin;
• forming pull-up doped epitaxial layers, in the fin on both sides of the gate structure in the pull-up transistor region;
• forming a first pull-down doped region, in the fin on one side of the gate structure in the pull-down transistor region, wherein the first pull-down doped region is connected to an adjacent pull-up doped epitaxial layer;
• and
• forming a second pull-down doped region, in the fin on another side of the gate structure in the pull-down transistor region, wherein the second pull-down doped region is formed by performing an ion-doped non-epitaxial layer process on the fin.