Spacer formation preventing gate bending

A semiconductor structure, comprising:

• a fin field-effect transistor (finFET) structure comprising:
• two or more spaced-apart gates formed on a fin substrate;
• and
• two or more spacers formed between the two or more spaced-apart gates, wherein each of the spacers comprises a first portion proximate a top surface of the fin substrate having a first width and a second portion above the first portion with a second width smaller than the first width;
• wherein a first distance between the first portions of pairs of spacers between adjoining pairs of the spaced-apart gates and a second distance between the second portions of the pairs of spacers between the adjoining pairs of the spaced-apart gates are substantially the same for each pair of spacers;
• wherein the two or more spaced-apart gates comprise at least a first adjoining pair of spaced-apart gates for at least a first pair of negative channel field-effect transistors (NFETs) and at least a second adjoining pair of spaced-apart gates for at least a second pair of positive channel field-effect transistors (PFETs);
• and
• wherein the second portions of the spacers surrounding the first adjoining pair of spaced-apart gates and the second portions of the spacers surrounding the second adjoining pair of spaced-apart gates each have substantially the same first width.

An integrated circuit comprising:

• a fin field-effect transistor (finFET) structure comprising:
• two or more spaced-apart gates formed on a fin substrate;
• and
• two or more spacers formed between the two or more spaced-apart gates, wherein each of the spacers comprises a first portion proximate a top surface of the fin substrate having a first width and a second portion above the first portion with a second width smaller than the first width;
• wherein a first distance between the first portions of pairs of spacers between adjoining pairs of the spaced-apart gates and a second distance between the second portions of the pairs of spacers between the adjoining pairs of the spaced-apart gates are substantially the same for each pair of spacers;
• wherein the two or more spaced-apart gates comprise at least a first adjoining pair of spaced-apart gates for at least a first pair of negative channel field-effect transistors (NFETs) and at least a second adjoining pair of spaced-apart gates for at least a second pair of positive channel field-effect transistors (PFETs), and
• wherein the second portions of the spacers surrounding the first adjoining pair of spaced-apart gates and the second portions of the spacers surrounding the second adjoining pair of spaced-apart gates each have substantially the same first width.