Forming switch circuit with controllable phase node ringing

A method for forming a switch circuit, comprising:

• forming an array of trench transistor cells in a semiconductor layer of a first conductivity type, the trench transistor cells being defined by trench gate structures, each of said gate trench structures including a trench formed in the semiconductor layer and an insulated gate electrode formed in the trench;
• forming first body regions of a second conductivity type that is opposite the first conductivity type in a first subset of the trench transistor cells, the first body regions and trenches of the first subset of the trench transistor cells being characterized by a first distance from a bottom of the first body regions to a bottom of the gate trenches in the first subset associated with a first reverse gate-to-drain capacitance (Crss);
• forming second body regions of the second conductivity type that is opposite the first conductivity type in a second subset of the trench transistor cells, the second body regions and trenches of the second subset of the trench transistor cells being characterized by a second distance from a bottom of the second body regions to a bottom of the gate trenches in the second subset associated with a second reverse gate-to-drain capacitance (Crss), wherein the second distance is greater than the first distance;
• and
• forming source regions in the array of trench transistor cells.