Semiconductor device having multiple gate pads

A method of gate oxide integrity (GOI) testing and electro-static discharge (ESD) protection network testing for semiconductor devices, the method comprising:

• with the semiconductor devices on a wafer, performing the GOI testing by applying a first voltage to a first gate pad of a semiconductor device of the semiconductor devices, the semiconductor device further comprising a gate comprising a gate oxide layer, wherein the first voltage is greater than the rated operational voltage of the gate oxide layer, the semiconductor device also comprising a second gate pad and a third gate pad that are electrically isolated from the first gate pad at all times during the GOI testing when the first voltage is applied to the first gate pad, wherein the second and third gate pads comprise a portion of the ESD protection network and wherein the first gate pad occupies less area of the semiconductor device than the third gate pad, wherein the ESD protection network is electrically isolated from the first gate pad and the first voltage during the GOI testing, and wherein the second gate pad occupies less area of the semiconductor device than the third gate pad;
• after completion of the GOI testing, removing the first voltage from the first gate pad;
• and
• after completion of the GOI testing and before an electrical connection between the first gate pad and the ESD protection network is formed, testing the ESD protection network, wherein said testing the ESD protection network comprises applying a second voltage to the ESD protection network, wherein the second gate pad and the third gate pad are electrically isolated from the first gate pad at all times during the testing of the ESD protection network.