US 10,256,225 B2 · Gate-less electrostatic discharge systems and methods for forming

Abstract

A gate-less electrostatic discharge (ESD) protection device is provided that can be formed in various complementary metal-oxide-semiconductor (CMOS) systems. The gate-less ESD event protection device includes a substrate, a first doped region formed in the substrate, a second doped region extending into the first doped region, a third doped region extending into the first doped region, a first node formed over a portion of the second doped region and coupled to a source terminal and a second node formed over the third doped region and coupled to a drain terminal. The gate-less ESD protection devices can be formed such that no gate electrode is formed and the gate-less ESD protection device does not include a gate terminal. Thus, an operating voltage range of the gate-less ESD protection device is not limited by gate oxide degradation.

Claims23

Dependent claims

A gate-less electrostatic discharge (ESD) event protection device comprising:

a substrate;
a first doped region comprising a first P-type region formed in the substrate;
a second doped region comprising a first N-type region extending into the first doped region;
a third doped region comprising a second N-type region extending into the first doped region;
a first node formed over a portion of the second doped region and coupled to a source terminal of a MOS-based structure;
and
a second node formed over the third doped region and coupled to a drain terminal of the MOS-based structure, wherein the device does not include a gate electrode;
a first low doped drain (LDD) layer extending into the first P-type region and adjacent to the first N-type region;
and
a second low doped drain (LDD) layer extending into the first P-type region and adjacent to the second N-type region.

7 more elements

An electrostatic discharge (ESD) event protection circuit comprising:

a first gate-less ESD event protection device having a first terminal coupled to an input/output (I/O) terminal of the circuit and a second terminal coupled to a reference voltage;
a second gate-less ESD protection device having a first terminal coupled to a power supply and a second terminal coupled to the reference voltage;
and
a circuit arrangement disposed between the first and second gate-less ESD event protection devices such that the first terminal of the first gate-less ESD event protection device is coupled to an input of the circuit arrangement and the first terminal of the second gate-less ESD event protection device is coupled to an output of the circuit arrangement, wherein each of the first and second gate-less ESD protection devices do not include a gate electrode;
wherein each of the first and second gate-less ESD protection devices comprises:
a substrate;
a first P-type region formed in the substrate;
a first N-type region extending into the first P-type region;
a second N-type region extending into the first P-type region;
a first node formed over the first N-type region and coupled to a source terminal of a MOS-based structure;
and
a second node formed over the second N-type region and coupled to a drain terminal of the MOS-based structure.

9 more elements

Dependencies are inferred from the claim text.

Gate-less electrostatic discharge systems and methods for forming

Life of this patent

Gate-less electrostatic discharge systems and methods for forming

Life of this patent

Abstract

Claims23