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US 10,256,190 B2Granted
Variable resistance memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorsYongkyu Lee, Gwanhyeob Koh, Boyoung Seo
Life of this patent
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Abstract
A variable resistance memory device includes different variable resistance patterns on different memory regions of a substrate. The different variable resistance patterns may be at different heights from the substrate and may have different intrinsic properties. The different variable resistance patterns may at least partially comprise separate memory cells that are each configured to function as a non-volatile memory cell or a random access memory cell, respectively.
Claims12
A device, comprising:
- a substrate including a first memory region and a second memory region;
- a first variable resistance pattern on the first memory region at a first height from the substrate, the first variable resistance pattern including
- a first shape,
- a first thickness, and
- a first material;
- and
- a second variable resistance pattern on the second memory region at a second height from the substrate, the second height less than the first height from the substrate, the second variable resistance pattern including
- a second shape that is different from the first shape,
- a second thickness that is different from the first thickness,
- a second material that is different from the first material,
- a sub-combination thereof, or
- a combination thereof;
- a first interconnection group on the substrate, the first interconnection group including a plurality of first interconnection patterns;
- a second interconnection group between the substrate and the first interconnection group, the second interconnection group including a plurality of second interconnection patterns;
- and
- a third interconnection group between the substrate and the second interconnection group, the third interconnection group including a plurality of third interconnection patterns,
- wherein the first interconnection group, the second interconnection group, and the third interconnection group are at different heights from the substrate,
- wherein the first variable resistance pattern is between the first interconnection group and the second interconnection group, and
- wherein the second variable resistance pattern is between the second interconnection group and the third interconnection group.
16 more elements
A device, comprising:
- a substrate including a first memory region and a second memory region;
- a first variable resistance pattern on the first memory region at a first height from the substrate;
- and
- a second variable resistance pattern on the second memory region at a second height from the substrate, the second height different from than the first height, the second variable resistance pattern including an intrinsic property that is different from a corresponding intrinsic property of the first variable resistance pattern;
- a first interconnection group on the substrate, the first interconnection group including a plurality of first interconnection patterns;
- a second interconnection group between the substrate and the first interconnection group, the second interconnection group including a plurality of second interconnection patterns;
- and
- a third interconnection group between the substrate and the second interconnection group, the third interconnection group including a plurality of third interconnection patterns,
- wherein the first interconnection group, the second interconnection group, and the third interconnection group are at different heights from the substrate,
- wherein the first variable resistance pattern is between the first interconnection group and the second interconnection group, and
- wherein the second variable resistance pattern is between the second interconnection group and the third interconnection group.
8 more elements
Dependencies are inferred from the claim text.