Hydrogen diffusion barrier structures for CMOS devices and method of making the same

A semiconductor structure comprising:

• a field effect transistor located on a semiconductor substrate;
• a silicon oxide liner contacting at least portions of top surfaces of active regions of the field effect transistor;
• a silicon nitride liner contacting a top surface and a sidewall of the silicon oxide liner;
• a gate cap dielectric overlying a gate electrode of the field effect transistor;
• a silicon nitride diffusion barrier layer including a planar bottom surface that contacts top surfaces of vertically extending portions of the silicon nitride liner and a top surface of the gate cap dielectric;
• a silicon oxide material portion overlying the silicon nitride diffusion barrier layer;
• and
• a gate contact via structure that extends through the silicon nitride diffusion barrier layer and the gate cap dielectric and contacts the gate electrode of the field effect transistor.

A method of forming a semiconductor structure, comprising:

• forming a field effect transistor on a semiconductor substrate, wherein the field effect transistor comprises active regions embedded in the semiconductor substrate and a gate electrode overlying the semiconductor substrate;
• forming a silicon oxide liner over the field effect transistor and on a top surface of the semiconductor substrate;
• forming at least one opening laterally enclosing an area through the silicon oxide liner, wherein the top surface of the semiconductor substrate is physically exposed within each of the at least one opening in the silicon oxide liner;
• forming a silicon nitride liner over the silicon oxide liner and on the top surface of the semiconductor substrate in a seal region defined between an inner periphery and an outer periphery of the at least one opening in the silicon oxide liner;
• forming a silicon oxide planarization layer including a planar top surface around the gate electrode and over portions of the silicon nitride liner that laterally surround the gate electrode;
• forming a silicon nitride diffusion barrier layer over the silicon oxide planarization layer and top surfaces of vertically extending portions of the silicon nitride liner;
• and
• forming a silicon oxide material portion over the silicon nitride diffusion barrier layer, wherein a combination of the silicon nitride liner and the silicon nitride diffusion barrier layer constitutes a hydrogen diffusion barrier structure that continuously extends from the seal region and over the field effect transistor.