Insulated epitaxial structures in nanosheet complementary field effect transistors

An integrated circuit structure comprising:

• a substrate;
• isolation elements extending into a surface of the substrate;
• source/drain regions of a first transistor contacting the isolation elements, wherein the isolation elements extend from the substrate to the source/drain regions of the first transistor;
• isolation layers contacting the source/drain regions of the first transistor;
• source/drain regions of a second transistor contacting the isolation layers, wherein the first transistor is positioned between the second transistor and the substrate, and wherein the isolation layers comprise insulators and are between the source/drain regions of the first transistor and the source/drain regions of the second transistor;
• a channel region of the first transistor contacting and extending between the source/drain regions of the first transistor;
• a channel region of the second transistor contacting and extending between the source/drain regions of the second transistor, wherein the channel region of the first transistor and the channel region of the second transistor extend parallel to the surface of the substrate;
• a gate conductor surrounding sides of the channel region of the first transistor and the channel region of the second transistor;
• and
• a liner dielectric electrically laterally adjacent the gate conductor,
• wherein the liner dielectric is different from the isolation layers and the isolation elements.

An integrated circuit structure comprising:

• isolation elements extending into a substrate;
• source/drain regions of a first transistor contacting the isolation elements, wherein the isolation elements extend from the substrate to the source/drain regions of the first transistor;
• isolation layers contacting the source/drain regions of the first transistor;
• source/drain regions of a second transistor contacting the isolation layers, wherein the first transistor is positioned between the second transistor and the substrate, and wherein the isolation layers are between the source/drain regions of the first transistor and the source/drain regions of the second transistor;
• a channel region of the first transistor contacting and extending between the source/drain regions of the first transistor;
• a channel region of the second transistor contacting and extending between the source/drain regions of the second transistor;
• and
• a gate conductor surrounding sides of the channel region of the first transistor and the channel region of the second transistor,
• wherein the source/drain regions of the second transistor are SiGe:B epitaxial growths on surfaces of the channel region of the second transistor.