Method for manufacturing a Si-based high-mobility CMOS device with stacked channel layers, and resulting devices

A method for manufacturing a Si-based high-mobility CMOS device, wherein a Ge or SixGe1-x channel layer and a III-V semiconductor channel layer are co-integrated on a silicon substrate, the method comprising the steps of:

• a) providing a silicon substrate having a first insulation layer on top and a trench extending through the insulation layer and into the silicon;
• b) manufacturing a germanium or silicon-germanium channel layer above the first insulation layer by means of, in sequence, depositing a first dummy layer of a sacrificial material above the first insulation layer and in the trench, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with germanium or silicon-germanium material by etching the sacrificial material via first holes made in the first oxide layer followed by selective area growth with the germanium or silicon-germanium material;
• c) manufacturing a second insulation layer above the germanium or silicon-germanium channel layer and uncovering the trench;
• and
• d) manufacturing a III-V semiconductor channel layer above the second insulation layer by means of, in sequence, depositing a second dummy layer of a sacrificial material above the second insulation layer and in the trench, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with III-V semiconductor material by etching the sacrificial material via second holes made in the second oxide layer followed by selective area growth with III-V semiconductor material.