US 10,256,150 B2 · Fabricating Fin-based split-gate high-drain-voltage transistor by work function tuning

Abstract

A method is presented for creating an asymmetrical split-gate structure. The method includes forming a first device, forming a second device, forming a first gate stack between a first set of spacers of the first device, and a second gate stack between a second set of spacers of the second device. The method further includes depositing a hard mask over the first and second gate stacks, etching a first section of the first gate stack to create a first gap and a second section of the second gate stack to create a second gap, and forming a third gate stack within the first gap of the first gate stack and within the second gap of the second gate stack such that dual gate stacks are defined for each of the first and second devices. The method further includes annealing the dual gate stacks to form replacement metal gate stacks.

Claims5

Dependent claims

A structure for creating an asymmetrical split-gate structure, the structure comprising:

a first device formed over a semiconductor substrate, the first device having first source/drain regions formed adjacent a first set of spacers;
a second device formed over the semiconductor substrate, the second device having second source/drain regions formed adjacent a second set of spacers;
a first replacement metal dual gate stacks formed between the first set of spacers of the first device;
a second replacement metal dual gate stacks formed between the second set of spacers of the second device;
wherein the dual replacement gate stacks of the first replacement metal dual gate stacks have different number of layers, and
wherein each gate stack of the first replacement metal dual gate stacks comprises a single conducting layer consisting of titanium nitride (TiN) and lanthanum oxide (La2O3).

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

15/477,575Filed 3 Apr 2017

Published

US 2018/0286760 A14 Oct 2018

Granted

9 Apr 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification22 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 30/0221
Of FETs having insulated gates [IGFET]: having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or…
H10D 64/01322
Characterised by the conductor: the conductor contacting the insulator having a lateral variation in doping, composition or deposition steps
H10D 64/667
Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes: the conductor comprising a layer of…

Fabricating Fin-based split-gate high-drain-voltage transistor by work function tuning

Life of this patent

Fabricating Fin-based split-gate high-drain-voltage transistor by work function tuning

Life of this patent

Abstract

Claims5