Method of manufacturing a semiconductor power package

A method of manufacturing a semiconductor power package, the method comprising:

• providing a pre-molded chip housing and an electrically conducting chip carrier cast-in-place in the pre-molded chip housing;
• bonding a power semiconductor chip on the electrically conducting chip carrier;
• and
• applying a covering material so as to embed the power semiconductor chip, the covering material having an elastic modulus less than an elastic modulus of a material of the pre-molded chip housing and/or a thermal conductivity greater than a thermal conductivity of the material of the pre-molded chip housing and/or a temperature stability greater than a temperature stability of the pre-molded chip housing;
• introducing into a compression molding tool an arrangement that comprises the electrically conducting chip carrier cast-in-place in the pre-molded chip housing with the power semiconductor chip bonded on the electrically conducting chip carrier and the covering material applied so as to embed the power semiconductor chip, the compression molding tool configured to perform a compression molding process and comprising a top cavity mold half, a bottom cavity mold half and spring-loaded chip housing clamp rings;
• closing the chip housing clamp rings to seal a mold cavity which includes the arrangement;
• moving the top cavity mold half and the bottom cavity mold half under pressure in a direction towards each other;
• and
• during the compression molding process, distributing the covering material throughout the entire mold cavity.