Method for fabricating a field effect transistor having a surrounding grid

A process for fabricating a gate-wrap-around field-effect transistor, comprising:

• providing a substrate surmounted with first and second nanowires made of semiconductor material extending in a same longitudinal direction and being arranged plumb with one another, each of the first and second nanowires having:
• a median portion, covered by a first material, and
• first and second ends that are arranged on either side of the median portion in said same longitudinal direction, a periphery of which being covered by respective first and second dielectric spacers made of a second material that is different from the first material, said first and second ends respectively having first and second exposed lateral faces;
• doping a portion of the first and second ends via said first and second lateral faces;
• depositing an amorphous silicon alloy on said first and second lateral faces of said first and second nanowires, followed by a step of crystallizing said amorphous silicon alloy;
• and
• depositing a metal on either side of the first and second nanowires to form first and second metal contacts that respectively make electrical contact with the doped portions of the first and second ends of the first and second nanowires.