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US 10,255,987 B1Granted
Margin test for one-time programmable memory (OTPM) array with common mode current source
AssigneeGlobalfoundries Inc.
InventorJohn A. Fifield
Life of this patent
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Abstract
The present disclosure relates to a structure which includes a current-mirror control node which is configured to adjust a current margin and provide the adjusted current margin to at least one one-time programmable memory (OTPM) cell.
Claims19
A structure comprising:
- a current-mirror control node which is configured to adjust a current margin and provide the adjusted current margin to at least one one-time programmable memory (OTPM) cell;
- and
- a twin-cell memory in the OTPM cell which is configured to be programmable using a plurality of write operations based on the adjusted current margin,
- wherein the twin-cell memory comprises a pair of NFET devices with different threshold voltages,
- the pair of NFET devices comprises a true NFET transistor and a complement NFET transistor, and
- a word line is connected to a gate of the true NFET transistor and a gate of the complement NFET transistor.
3 more elements
A structure comprising:
- a twin-cell NFET memory in a one-time programmable memory (OTPM) cell which is configured to program at least one write operation based on a current margin;
- and
- a current sense amplifier which is configured to adjust the current margin and provide the adjusted current margin to the twin-cell memory based on a current mirror control node,
- wherein the twin-cell NFET memory comprises a pair of NFET devices with different threshold voltages,
- the pair of NFET devices comprises a true NFET transistor and a complement NFET transistor, and
- a word line is connected to a gate of the true NFET transistor and a gate of the complement NFET transistor.
3 more elements
A method, comprising:
- adjusting a current margin in a current-mirror control node based on a plurality of input margin signals;
- providing the adjusted current margin to a twin-cell memory through a true bit line (BLT) and a complement bit line (BLC);
- sensing a current differential of the twin-cell memory;
- and
- latching a differential voltage based on the sensed current differential of the twin-cell memory,
- wherein the twin-cell memory comprises a pair of NFET devices with different threshold voltages,
- the pair of NFET devices comprises a true NFET transistor and a complement NFET transistor, and
- a word line is connected to a gate of the true NFET transistor and a gate of the complement NFET transistor.
5 more elements
Dependencies are inferred from the claim text.