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US 10,255,973 B2Granted
Memory device and method of operation thereof
AssigneeSTMicroelectronics S.r.l.
InventorsDavide Manfre, Cesare Torti, Fabio Enrico Carlo Disegni
Life of this patent
Estimating the term…
Abstract
An embodiment memory device includes a memory array having a plurality of bit lines, a low-voltage connection path configured to connect, in an operational phase of the device, an access terminal to a selected local bit line of the plurality of bit lines, and a high-voltage connection path configured to connect, in the operational phase of the device, the access terminal to the selected local bit line, in parallel with the low-voltage connection path.
Claims21
A device, comprising:
- a memory array having a plurality of bit lines;
- a low-voltage connection path configured to connect, in an operational phase of the device, an access terminal to a selected local bit line of the plurality of bit lines;
- and
- a high-voltage connection path configured to connect, in the operational phase of the device, the access terminal to the selected local bit line, in parallel with the low-voltage connection path, wherein the low-voltage connection path comprises a read switching stage having a control terminal configured to receive an access enable signal, and wherein the high-voltage connection path comprises a modify switching stage having a control terminal configured to receive the access enable signal, wherein the modify switching stage comprises a modify switch and a uncoupling switch, the modify switch being configured to receive the access enable signal and couple the access terminal to the selected local bit line depending on the access enable signal, the uncoupling switch being configured to receive the access enable signal and uncouple a load element from the selected local bit line.
1 more element
A method for operating a phase-change memory device having a memory array comprising a plurality of bit lines, the method comprising:
- connecting, in an operational phase of the phase-change memory device, an access terminal of the phase-change memory device to a selected bit line of the plurality of bit lines through a low-voltage connection path;
- connecting, in the operational phase of the phase-change memory device, the access terminal to the selected bit line through a high-voltage connection path in parallel with the low-voltage connection path;
- receiving an access enable signal having an enable logic state and enabling the high-voltage connection path and the low-voltage connection path in presence of the enable logic state;
- and
- generating an addressing signal, generating a read selection signal and a modify selection signal based on the addressing signal and the access enable signal, supplying the read selection signal to a read switch arranged on the low-voltage connection path, and supplying the modify selection signal to a modify switch arranged on the high-voltage connection path.
2 more elements
A device, comprising:
- a memory cell coupled to a selected local bit line;
- a first switching stage configured to couple a memory access terminal to the selected local bit line by a first connection path in response to an access enable signal;
- and
- a second switching stage configured to couple the memory access terminal to the selected local bit line by a second connection path in parallel to the first connection path and in response to the access enable signal, wherein the second switching stage comprises a modify switch and a uncoupling switch, the modify switch being configured to receive the access enable signal and couple the memory access terminal to the selected local bit line depending on the access enable signal, the uncoupling switch being configured to receive the access enable signal and uncouple a load element from the selected local bit line when the modify switch couples the memory access terminal to the selected local bit line.
1 more element
A method for operating a phase-change memory device having a memory array comprising a plurality of bit lines, the method comprising:
- connecting, in an operational phase of the phase-change memory device, an access terminal of the phase-change memory device to a selected bit line of the plurality of bit lines through a low-voltage connection path;
- connecting, in the operational phase of the phase-change memory device, the access terminal to the selected bit line through a high-voltage connection path in parallel with the low-voltage connection path;
- receiving an access enable signal having an enable logic state and enabling the high-voltage connection path and the low-voltage connection path in presence of the enable logic state;
- and
- generating an addressing signal, generating a read selection signal based on the addressing signal and on the access enable signal, supplying the read selection signal to a read switch arranged on the low-voltage connection path, and supplying the addressing signal and the access enable signal to a modify switch arranged on the high-voltage connection path.
2 more elements
Dependencies are inferred from the claim text.