Memory system and control method of memory system
AssigneeToshiba Memory Corporation
InventorNobuaki Sato
Life of this patent
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Abstract
A memory system includes a non-volatile memory and a controller configured to perform a read re-try in response to a failed normal read. The read re-try includes a first read of data at a first read voltage, a second read of data at a second read voltage obtained by shifting the first read voltage by a first shift amount, which is determined according to a bit count value obtained by counting a number of predetermined bit values in the first read, a third read of data carried out a plurality of times at a plurality of third read voltages, wherein each of the plurality of third read voltages are shifted from each other by a second shift amount, and a final read of data at a read voltage that is set closer to the second read voltage than the first read voltage.
Claims20
A memory system comprising:
- a non-volatile memory including a plurality of memory cells;
- and
- a controller configured to perform a read re-try in response to a failed normal read, wherein the read re-try includes
- a first read processing of reading data from the plurality of memory cells at a first read voltage,
- a second read processing of reading data from the plurality of memory cells at a second read voltage obtained by shifting the first read voltage by a first shift amount, which is determined according to a bit count value obtained by counting a number of predetermined bit values in the data read in the first read processing,
- a third read processing of reading data from the plurality of memory cells a plurality of times at a plurality of third read voltages and obtaining a bit count value for each of the third read voltages, wherein each of the plurality of third read voltages are shifted from each other by a second shift amount, and
- a final read processing of reading data from the plurality of memory cells at a read voltage that is set closer to the second read voltage than the first read voltage.
A method of performing a read re-try in response to a failed normal read in a memory system including a non-volatile memory including a plurality of memory cells, said method comprising:
- a first read processing of reading data from the plurality of memory cells at a first read voltage;
- a second read processing of reading data from the plurality of memory cells at a second read voltage obtained by shifting the first read voltage by a first shift amount, which is determined according to a bit count value obtained by counting a number of predetermined bit values in the data read in the first read processing;
- a third read processing of reading data from the plurality of memory cells a plurality of times at a plurality of third read voltages and obtaining a bit count value for each of the third read voltages, wherein each of the plurality of third read voltages are shifted from each other by a second shift amount;
- and
- a final read processing of reading data from the plurality of memory cells at a read voltage that is set closer to the second read voltage than the first read voltage.
Dependencies are inferred from the claim text.