Semiconductor device

A semiconductor device comprising:

• a memory array which includes a plurality of memory cells arranged in a matrix;
• word lines which are provided and correspond respectively to rows of the memory array;
• a bit line pair which is provided and corresponds to columns of the memory array;
• word line drivers which are coupled to ends of the word lines, and activate the word lines by coupling the one ends of the word lines to a first power source, when a corresponding row is selected;
• and
• assist drivers which are coupled to other ends of the word lines, and couple the other ends of the word lines to the first power source in accordance with a voltage of the other ends of the word lines,
• wherein each of the assist drivers includes:
• a PMOS transistor provided between a power source and the other end of each of the word lines;
• and
• a delay circuit coupled to the other end of the word line and a NAND circuit having one input coupled to the other end of the word line, other input receiving an output of the delay circuit, and an output coupled to the gate of the PMOS transistor,
• wherein the memory cell includes:
• a first load transistor electrically coupled between a first power node and a first node;
• a first drive transistor electrically coupled between the first node and a second power node;
• a first access transistor electrically coupled between the first node and one of the bit line pairs;
• a second load transistor electrically coupled between the first power node and a second node;
• a second drive transistor electrically coupled between the second node and the second power node;
• a second access transistor electrically coupled between the second node and the other bit line of the bit line pairs;
• a first and a second P-well;
• an N-well;
• and
• a first to fourth active regions,
• wherein the N-well is arranged between the first and the second P-well to be adjacent to each other,
• wherein the second and third active regions are formed on the N-well,
• wherein the first and fourth active regions are formed on the first and second P-wells respectively,
• wherein the second active region is arranged between the first and third active regions,
• wherein the third active region is arranged between the second and fourth active regions,
• wherein the first drive transistor and the first access transistor are formed on the first active region,
• wherein the first load transistor is formed on the second active region,
• wherein the second load transistor is formed on the third active region,
• wherein the second access transistor and the second drive transistor are formed on the fourth active region,
• wherein gate electrodes of the first load transistor and the first drive transistor are formed of a first metal line, and
• wherein gate electrodes of the second load transistor and the second drive transistor are formed of the second metal line.